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Difference between revisions of "intel/core i3/i3-6006u"
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{{intel title|Core i3-6006U}}
 
{{intel title|Core i3-6006U}}
−
{{mpu
+
{{chip
−
| name               = Intel Core i3-6006U
+
|name=Core i3-6006U
−
| no image           = Yes
+
|image=skylake u (front; standard).png
−
| image              =
+
|designer=Intel
−
| image size          =
+
|manufacturer=Intel
−
| caption            =  
+
|model number=i3-6006U
−
| designer           = Intel
+
|part number=FJ8066201931106
−
| manufacturer       = Intel
+
|part number 2=FJ8066202498906
−
| model number       = i3-6006U
+
|s-spec=SR2UW
−
| part number         = FJ8066201931106
+
|s-spec 2=SR2JG
−
| part number 3      =  
+
|market=Mobile
−
| market             = Desktop
+
|first announced=November 10, 2016
−
| first announced     = November 10, 2016
+
|first launched=November 10, 2016
−
| first launched     = November 10, 2016
+
|last order=March 15, 2019
−
| last order         =  
+
|last shipment=September 30, 2019
−
| last shipment       =  
+
|release price=$281.00
−
| release price       = $281.00
+
|family=Core i3
−
 
+
|series=i3-6000
−
| family             = Core i3
+
|locked=Yes
−
| series             = 6000
+
|frequency=2,000 MHz
−
| locked             = Yes
+
|bus type=OPI
−
| frequency         = 2,000 MHz
+
|bus rate=4 GT/s
−
| bus type           = DMI 3.0
+
|clock multiplier=20
−
| bus speed          =  
+
|isa=x86-64
−
| bus rate           = 4 GT/s
+
|isa family=x86
−
| clock multiplier   = 20
+
|microarch=Skylake
−
| s-spec            = SR2UW
+
|core name=Skylake U
−
 
+
|core family=6
−
| isa family         = x86
+
|core model=78
−
| isa                = x86-64
+
|core stepping=D1
−
| microarch          = Skylake  
+
|core stepping 2=K1
−
| platform          =  
+
|process=14 nm
−
| core name          = Skylake U
+
|transistors=1,750,000,000
−
| core stepping     = D1
+
|technology=CMOS
−
| process           = 14 nm
+
|die area=98.57 mm²
−
| die size          =  
+
|die length=10.3 mm
−
| word size         = 64 bits
+
|die width=9.57 mm
−
| core count         = 2
+
|mcp=Yes
−
| thread count       = 4
+
|die count=2
−
| max cpus           = 1
+
|word size=64 bit
−
| max memory         = 32 GB
+
|core count=2
−
 
+
|thread count=4
−
| electrical          = Yes
+
|max cpus=1
−
| sdp                =  
+
|max memory=32 GiB
−
| tdp                 = 15 W
+
|v core min=0.55 V
−
| ctdp down          =  
+
|v core max=1.52 V
−
| ctdp down frequency =
+
|tdp=15 W
−
| ctdp up            =
+
|tjunc min=0 °C
−
| ctdp up frequency  =
+
|tjunc max=100 °C
−
| temp max           = 100 °C
+
|tstorage min=-25 °C
−
| temp min           = 0 °C
+
|tstorage max=125 °C
−
 
+
|package module 1={{packages/intel/fcbga-1356}}
−
| packaging          = Yes
 
−
| package            = FCBGA-1356
 
−
| package type      = FCBGA
 
−
| package pitch      =
 
−
| package size      = 42mm x 24mm x 1.3mm
 
−
| socket            = BGA-1356
 
−
| socket type        = BGA
 
 
}}
 
}}
−
'''Core i3-6006U''' is an ultra-low power {{arch|64}} [[x86]] [[dual-core]] performance [[microprocessor]] introduced by [[Intel]] in late 2016. This processor, which is based on the {{intel|Skylake}} microarchitecture and manufactured in [[14 nm process]], has a base frequency of 2 GHz with a TDP of 15 W. This processor incorporates the {{intel|HD Graphics 520}} [[GPU]] clocked at 300 MHz with a max frequency of 900 GHz.
+
'''Core i3-6006U''' is a {{arch|64}} [[dual-core]] entry-level performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2016]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 2 GHz. The i3-6006U has a TDP of 15 W. This chip incorporates the {{intel|HD Graphics 520}} GPU operating at 300 MHz with a burst frequency of 900 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
  
 
== Cache ==
 
== Cache ==
 
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
−
{{cache info
+
{{cache size
 +
|l1 cache=128 KiB
 
|l1i cache=64 KiB
 
|l1i cache=64 KiB
 
|l1i break=2x32 KiB
 
|l1i break=2x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
−
|l1i extra=(per core, write-back)
 
 
|l1d cache=64 KiB
 
|l1d cache=64 KiB
 
|l1d break=2x32 KiB
 
|l1d break=2x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
−
|l1d extra=(per core, write-back)
+
|l1d policy=write-back
 
|l2 cache=512 KiB
 
|l2 cache=512 KiB
 
|l2 break=2x256 KiB
 
|l2 break=2x256 KiB
 
|l2 desc=4-way set associative
 
|l2 desc=4-way set associative
−
|l2 extra=(per core, write-back)
+
|l2 policy=write-back
 
|l3 cache=3 MiB
 
|l3 cache=3 MiB
−
|l3 desc=shared
+
|l3 break=2x1.5 MiB
 +
|l3 policy=write-back
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2133
 +
|type 2=LPDDR3-1866
 +
|type 3=DDR3L-1600
 +
|ecc=No
 +
|max mem=32 GiB
 +
|controllers=1
 +
|channels=2
 +
|max bandwidth=31.79 GiB/s
 +
|bandwidth schan=15.89 GiB/s
 +
|bandwidth dchan=31.79 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 12
 +
| pcie config        = 1x4
 +
| pcie config 2      = 2x2
 +
| pcie config 3      = 1x2+2x1
 +
| pcie config 4      = 4x1
 
}}
 
}}
  
 
== Graphics ==
 
== Graphics ==
−
{{integrated graphic
+
{{integrated graphics
−
| gpu               = Intel HD Graphics 520
+
| gpu                 = HD Graphics 520
−
| device id         = 0x1916
+
| device id           = 0x1916
−
| displays           = 3
+
| designer            = Intel
−
| frequency         = 300 MHz
+
| execution units    = 24
−
| max frequency     = 900 GHz
+
| max displays       = 3
−
| max memory         = 32 GB
+
| max memory          = 32 GiB
−
| output edp         = Yes
+
| frequency           = 300 MHz
−
| output dp         = Yes
+
| max frequency       = 900 MHz
−
| output hdmi       = Yes
+
 
−
| output vga         =  
+
| output crt          =
−
| output dvi         = Yes
+
| output sdvo         =  
 +
| output dsi          =
 +
| output edp         = Yes
 +
| output dp           = Yes
 +
| output hdmi         = Yes
 +
| output vga         =  
 +
| output dvi         = Yes
 +
 
 
| directx ver        = 12
 
| directx ver        = 12
 
| opengl ver        = 4.4
 
| opengl ver        = 4.4
Line 109: Line 134:
 
| max res vga freq  =  
 
| max res vga freq  =  
  
−
| intel quick sync   = Yes
+
| features            = Yes
−
| intel intru 3d     = Yes
+
| intel quick sync     = Yes
−
| intel insider     = Yes
+
| intel intru 3d       = Yes
−
| intel widi         = Yes
+
| intel insider       =  
−
| intel fdi         =  
+
| intel widi           =  
−
| intel clear video = Yes
+
| intel fdi           =  
−
}}
+
| intel clear video   = Yes
−
 
+
| intel clear video hd = Yes
−
== Memory controller ==
 
−
{{integrated memory controller
 
−
| type              = DDR3L-1333
 
−
| type 2            = DDR3L-1600
 
−
| type 3            = DDR4-1866
 
−
| type 4            = DDR4-2133
 
−
| controllers        = 1
 
−
| channels          = 2
 
−
| ecc support        =
 
−
| max bandwidth      = 31.79 GiB/s
 
−
| bandwidth schan    =
 
−
| bandwidth dchan    =
 
−
| bandwidth tchan    =
 
−
| bandwidth qchan    =
 
−
| max memory        = 32 GiB
 
−
}}
 
−
 
 
−
== Expansions ==
 
−
{{mpu expansions
 
−
| pcie revision      = 3.0
 
−
| pcie lanes        = 12
 
−
| pcie config        = 1x4
 
−
| pcie config 1      = 2x2
 
−
| pcie config 2      = 1x2+2x1
 
−
| pcie config 3      = 4x1
 
−
| usb revision      =
 
−
| usb revision 2    =
 
−
| usb ports          =
 
−
| sata ports        =
 
−
| integrated lan    =
 
−
| uart              =
 
−
| gp io              =  
 
 
}}
 
}}
 +
{{skylake hardware accelerated video table|col=1}}
  
 
== Features ==  
 
== Features ==  
−
{{mpu features
+
{{x86 features
−
| em64t      = Yes
+
|real=Yes
−
| nx         = Yes
+
|protected=Yes
−
| txt        =  
+
|smm=Yes
−
| tsx        =  
+
|fpu=Yes
−
| vpro        =  
+
|x8616=Yes
−
| ht          = Yes
+
|x8632=Yes
−
| tbt1        =
+
|x8664=Yes
−
| tbt2        =  
+
|nx=Yes
−
| bpt        =  
+
|mmx=Yes
−
| vt-x        = Yes
+
|emmx=Yes
−
| vt-d        = Yes
+
|sse=Yes
−
| ept        = Yes
+
|sse2=Yes
−
| mmx        = Yes
+
|sse3=Yes
−
| sse        = Yes
+
|ssse3=Yes
−
| sse2        = Yes
+
|sse41=Yes
−
| sse3        = Yes
+
|sse42=Yes
−
| ssse3      = Yes
+
|sse4a=No
−
| sse4        = Yes
+
|avx=Yes
−
| sse4.1      = Yes
+
|avx2=Yes
−
| sse4.2      = Yes
+
|avx512f=No
−
| aes        = Yes
+
|avx512cd=No
−
| pclmul      = Yes
+
|avx512er=No
−
| avx        = Yes
+
|avx512pf=No
−
| avx2        = Yes
+
|avx512bw=No
−
| bmi        = Yes
+
|avx512dq=No
−
| bmi1        = Yes
+
|avx512vl=No
−
| bmi2        = Yes
+
|avx512ifma=No
−
| f16c        = Yes
+
|avx512vbmi=No
−
| fma3        = Yes
+
|avx5124fmaps=No
−
| mpx         = Yes
+
|avx512vnni=No
−
| sgx         = Yes
+
|avx5124vnniw=No
−
| eist        = Yes
+
|avx512vpopcntdq=No
−
| secure key  = Yes
+
|abm=Yes
−
| os guard    = Yes
+
|tbm=No
−
| intel at    =  
+
|bmi1=Yes
−
| intel ipt  = Yes
+
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=Yes
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=Yes
 +
|sba=No
 +
|mwt=Yes
 +
|sipp=No
 +
|att=No
 +
|ipt=Yes
 +
|tsx=No
 +
|txt=No
 +
|ht=Yes
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=Yes
 +
|securekey=Yes
 +
|osguard=Yes
 +
|intqat=No
 +
|dlboost=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 
}}
 
}}

Latest revision as of 01:21, 16 January 2019

Edit Values
Core i3-6006U
skylake u (front; standard).png
General Info
DesignerIntel
ManufacturerIntel
Model Numberi3-6006U
Part NumberFJ8066201931106,
FJ8066202498906
S-SpecSR2UW, SR2JG
MarketMobile
IntroductionNovember 10, 2016 (announced)
November 10, 2016 (launched)
End-of-lifeMarch 15, 2019 (last order)
September 30, 2019 (last shipment)
Release Price$281.00
ShopAmazon
General Specs
FamilyCore i3
Seriesi3-6000
LockedYes
Frequency2,000 MHz
Bus typeOPI
Bus rate4 GT/s
Clock multiplier20
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake
Core NameSkylake U
Core Family6
Core Model78
Core SteppingD1, K1
Process14 nm
Transistors1,750,000,000
TechnologyCMOS
Die98.57 mm²
10.3 mm × 9.57 mm
MCPYes (2 dies)
Word Size64 bit
Cores2
Threads4
Max Memory32 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore0.55 V-1.52 V
TDP15 W
Tjunction0 °C – 100 °C
Tstorage-25 °C – 125 °C
Packaging
PackageFCBGA-1356 (BGA)
Dimension42 mm x 24 mm x 1.3 mm
Pitch0.65 mm
Ball Count1356
Ball CompSAC405
InterconnectBGA-1356

Core i3-6006U is a 64-bit dual-core entry-level performance x86 mobile microprocessor introduced by Intel in late 2016. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2 GHz. The i3-6006U has a TDP of 15 W. This chip incorporates the HD Graphics 520 GPU operating at 300 MHz with a burst frequency of 900 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
  2x1.5 MiB write-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133, LPDDR3-1866, DDR3L-1600
Supports ECCNo
Max Mem32 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes12
Configs1x4, 2x2, 1x2+2x1, 4x1


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics 520
DesignerIntelDevice ID0x1916
Execution Units24Max Displays3
Max Memory32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
Frequency300 MHz
0.3 GHz
300,000 KHz
Burst Frequency900 MHz
0.9 GHz
900,000 KHz
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4096x2304 @24 Hz
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.3
HDMI1.4a
Additional Features
Intel Quick Sync Video
Intel InTru 3D
Intel Clear Video
Intel Clear Video HD

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
EISTEnhanced SpeedStep Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Flex MemoryFlex Memory Access
ISRTSmart Response Technology
MWTMy WiFi Technology
IPTIdentity Protection Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i3/i3-6006u&oldid=86176"
Facts about "Core i3-6006U - Intel"
RDF feed
device id0x1916 +
has featureintegrated gpu +
integrated gpuIntel HD Graphics 520 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu max frequency900,000 MHz (900 GHz, 900,000,000 KHz) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ descriptionshared +
l3$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +