Latest revision as of 15:10, 13 December 2017

Edit Values
Cavium CN3010-300 CP
General Info
Designer	Cavium
Manufacturer	TSMC
Model Number	CN3010-300 CP
Part Number	CN3010-300BG525-CP
Market	Embedded
Introduction	January 30, 2006 (announced) May 1, 2006 (launched)
Release Price	$39
General Specs
Family	OCTEON
Series	CN3000
Frequency	300 MHz
Microarchitecture
ISA	MIPS64 (MIPS)
Microarchitecture	cnMIPS
Core Name	cnMIPS
Process	130 nm
Technology	CMOS
Word Size	64 bit
Cores	1
Threads	1
Max Memory	2 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Power dissipation	2 W

The CN3010-300 CP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2006. This processor, which incorporates a single cnMIPS core, operates at 300 MHz and dissipates 2 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the CN3005 equivalent, double DDR2 memory access, as well as support for TDM/PCM (VoIP support).

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 24 KiB 24,576 B 0.0234 MiB L1I$ 16 KiB 16,384 B 0.0156 MiB 1x16 KiB 2-way set associative   L1D$ 8 KiB 8,192 B 0.00781 MiB 1x8 KiB 64-way set associative Write-through L2$ 128 KiB 0.125 MiB 131,072 B 1.220703e-4 GiB     1x128 KiB 4-way set associative

Memory controller[edit]

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR2-533 Supports ECC Yes Max Mem 2 GiB Controllers 1 Channels 1 Width 32 bit Max Bandwidth 1.986 GiB/s 2,033.664 MiB/s 2.132 GB/s 2,132.451 MB/s 0.00194 TiB/s 0.00213 TB/s Bandwidth Single 1.986 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

	Expansion Options
	PCI Width 32 bit Clock 66.66 MHz Rate 254.31 MiB/s Features host or slave USB Revision 2.0 Ports 1 Rate 60 MB/s Features host / PHY UART Ports 2 GP I/O Yes

Networking[edit]

[Edit/Modify Network Info]

	Networking
	MII RGMII Yes (Ports: 3) TDM/PCM Yes

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

	Hardware Accelerators
	Networking TCP Yes QoS Yes

Block diagram[edit]

Datasheet[edit]

• OCTEON CN30XX Processors Product Brief