Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/xeon e5/e5-2689a v4"
m (Bot: moving all {{mpu}} to {{chip}}) |
|||
| (4 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
{{intel title|Xeon E5-2689A v4}} | {{intel title|Xeon E5-2689A v4}} | ||
| − | {{ | + | {{chip |
| name = Xeon E5-2689A v4 | | name = Xeon E5-2689A v4 | ||
| no image = Yes | | no image = Yes | ||
| Line 10: | Line 10: | ||
| model number = E5-2689A v4 | | model number = E5-2689A v4 | ||
| part number = | | part number = | ||
| − | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Server | | market = Server | ||
| first announced = June 20, 2016 | | first announced = June 20, 2016 | ||
| Line 62: | Line 62: | ||
| max memory = 1,536 GiB | | max memory = 1,536 GiB | ||
| − | + | ||
| v core = 1.82 V | | v core = 1.82 V | ||
| v core tolerance = | | v core tolerance = | ||
| Line 132: | Line 132: | ||
== Expansions == | == Expansions == | ||
| − | {{ | + | {{expansions |
| pcie revision = 3.0 | | pcie revision = 3.0 | ||
| pcie lanes = 40 | | pcie lanes = 40 | ||
| Line 141: | Line 141: | ||
== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| em64t = Yes | | em64t = Yes | ||
| nx = Yes | | nx = Yes | ||
Latest revision as of 16:28, 13 December 2017
| Edit Values | |
| Xeon E5-2689A v4 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | E5-2689A v4 |
| S-Spec | SR2KZ |
| Market | Server |
| Introduction | June 20, 2016 (announced) June 20, 2016 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Xeon E5 |
| Series | E5-2000 |
| Locked | Yes |
| Frequency | 3,400 MHz |
| Turbo Frequency | Yes |
| Bus type | QPI |
| Bus speed | 4,800 MHz |
| Bus rate | 2 × 9.6 GT/s |
| Clock multiplier | 34 |
| CPUID | 406F1 |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Broadwell |
| Platform | Grantley EP 2S |
| Chipset | C610 Series |
| Core Name | Broadwell EP |
| Core Family | 6 |
| Core Model | 4F |
| Core Stepping | R0 |
| Process | 14 nm |
| Transistors | 3,200,000,000 |
| Technology | CMOS |
| Die | 246.24 mm² |
| Word Size | 64 bit |
| Cores | 8 |
| Threads | 16 |
| Max Memory | 1,536 GiB |
| Multiprocessing | |
| Max SMP | 2-Way (Multiprocessor) |
| Electrical | |
| Vcore | 1.82 V |
| VI/O | 1.2 V ± 3% |
| TDP | 145 W |
| Tcase | 0 °C – ? °C |
| Tstorage | -25 °C – 125 °C |
The Xeon E5-2689A v4 is a 64-bit octa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for 2S environments. Operating at 3.4 GHz with a turbo boost frequency of ? GHz for a single active core, this MPU has a TDP of 145 W and is manufactured on a 14 nm process (based on Broadwell).
This microprocessor is OEM only.
Cache[edit]
- Main article: Broadwell § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 256 KiB 262,144 B 0.25 MiB |
8x32 KiB 8-way set associative (per core, write-back) |
| L1D$ | 256 KiB 262,144 B 0.25 MiB |
8x32 KiB 8-way set associative (per core, write-back) |
| L2$ | 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB |
8x256 KiB 8-way set associative (per core, write-back) |
| L3$ | 20 MiB 20,480 KiB 20,971,520 B 0.0195 GiB |
8x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics[edit]
This microprocessor has no integrated graphics processing unit.
Memory controller[edit]
| Integrated Memory Controller | |
| Type | DDR4-2400 |
| Controllers | 1 |
| Channels | 4 |
| ECC Support | Yes |
| Max bandwidth | 71.53 GiB/s |
| Bandwidth (single) | 17.88 GiB/s |
| Bandwidth (dual) | 35.76 GiB/s |
| Max memory | 1,536 GiB |
| Physical Address Extensions | 46 bit |
Expansions[edit]
 |
Expansion Options
|
|||||||
|
||||||||
Features[edit]
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
|
|||||||||||||||||||||||||||||||||||||||
|
||||||||||||||||||||||||||||||||||||||||
Facts about "Xeon E5-2689A v4 - Intel"
| l1d$ description | 8-way set associative + |
| l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| l3$ description | 20-way set associative + |
| l3$ size | 20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) + |