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Difference between revisions of "intel/core i5/i5-520m"
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{{intel title|Core i5-520M}}
 
{{intel title|Core i5-520M}}
−
{{mpu
+
{{chip
 
| name                = Intel Core i5-520M
 
| name                = Intel Core i5-520M
 
| no image            = yes
 
| no image            = yes
Line 10: Line 10:
 
| model number        = i5-520M
 
| model number        = i5-520M
 
| part number        = BX80617I5520M
 
| part number        = BX80617I5520M
−
| part number 1       = CP80617004119AE
+
| part number 2       = CP80617004119AE
−
| part number 2       = CN80617004119AE
+
| part number 3       = CN80617004119AE
 
| market              = Mobile
 
| market              = Mobile
 +
| market 2            = Embedded
 
| first announced    = January 7, 2010
 
| first announced    = January 7, 2010
 
| first launched      = January 7, 2010
 
| first launched      = January 7, 2010
Line 38: Line 39:
 
| cpuid              = 0x20655
 
| cpuid              = 0x20655
  
 +
| isa family          = x86
 +
| isa                = x86-64
 
| microarch          = Westmere
 
| microarch          = Westmere
 
| platform            = Calpella
 
| platform            = Calpella
Line 58: Line 61:
 
| max memory          = 8 GiB
 
| max memory          = 8 GiB
  
−
| electrical          = Yes
+
 
 
| v core              =  
 
| v core              =  
 
| v core tolerance    =  
 
| v core tolerance    =  
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== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=DDR3-1066
+
|type=DDR3-1280
 
|ecc=No
 
|ecc=No
 
|max mem=8 GiB
 
|max mem=8 GiB
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|avx=No
 
|avx=No
 
|avx2=No
 
|avx2=No
−
|avx512=No
+
 
 
|abm=No
 
|abm=No
 
|tbm=No
 
|tbm=No

Latest revision as of 09:47, 24 March 2019

Edit Values
Intel Core i5-520M
General Info
DesignerIntel
ManufacturerIntel
Model Numberi5-520M
Part NumberBX80617I5520M,
CP80617004119AE,
CN80617004119AE
S-SpecSLBNB, SLBNA, SLBU3, SLBU4
MarketMobile, Embedded
IntroductionJanuary 7, 2010 (announced)
January 7, 2010 (launched)
End-of-lifeOctober 19, 2012 (last order)
January 18, 2013 (last shipment)
Release Price$225
ShopAmazon
General Specs
FamilyCore i5
Seriesi5-500
LockedYes
Frequency2399.99 MHz
Turbo FrequencyYes
Turbo Frequency2,933.33 MHz (1 core),
2,666.66 MHz (2 cores)
Bus typeDMI 1.0
Bus rate1 × 2.5 GT/s
Clock multiplier18
CPUID0x20655
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureWestmere
PlatformCalpella
ChipsetIbex Peak
Core NameArrandale
Core Family6
Core Model37
Core SteppingK0, C2
Process32 nm
Transistors382,000,000
TechnologyCMOS
Die81 mm²
Word Size64 bit
Cores2
Threads4
Max Memory8 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP35 W
Tjunction0 °C – 105 °C
Tstorage-25 °C – 125 °C
Packaging
PackagerPGA-988A (rPGA)rPGA988A.svg
Dimension36 mm x 35 mm x 2.12 mm
Pitch1 mm
Pin Count988
SocketSocket-G1 (PGA)
PackageBGA-1288 (BGA)BGA-1288.svg
Dimension34 mm x 28 mm x 2.1 mm
Pitch0.7 mm
Pin Count1288

Core i5-520M is a 64-bit x86 dual-core mobile microprocessor introduced by Intel in 2010. This processor, which is based on the Westmere microarchitecture (Arrandale core), is manufactured on a 32 nm process. This MPU operates at a base frequency of 2.40 GHz with a Turbo Boost frequency of 2.93 GHz and a TDP of 35 W. This processor incorporated the HD Graphics (Ironlake) IGP on the same package operating at a base frequency of 500.00 MHz and a burst frequency of 766.00 MHz.

Cache[edit]

Main article: Westmere § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associativewrite-back
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB8-way set associativewrite-back
L3$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
  2x1.5 MiB12-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1280
Supports ECCNo
Max Mem8 GiB
Controllers1
Channels2
Max Bandwidth15.88 GiB/s
16,261.12 MiB/s
17.051 GB/s
17,051.02 MB/s
0.0155 TiB/s
0.0171 TB/s
Bandwidth
Single 7.942 GiB/s
Double 15.88 GiB/s
Physical Address (PAE)36 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes16
Configs1x16


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics (Ironlake)
DesignerIntelDevice ID0x0046
Execution Units12Max Displays2
Frequency500 MHz
0.5 GHz
500,000 KHz
Burst Frequency766 MHz
0.766 GHz
766,000 KHz
Standards
DirectX10.1
OpenGL2.1
Additional Features
Intel Flexible Display Interface (FDI)
Intel Clear Video
Intel Clear Video HD

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AESAES Encryption Instructions
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 1.0Turbo Boost Technology 1.0
EISTEnhanced SpeedStep Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
Flex MemoryFlex Memory Access
FMAFast Memory Access (w\ GMCH)
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i5/i5-520m&oldid=87237"
Facts about "Core i5-520M - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Core i5-520M - Intel#package + and Core i5-520M - Intel#io +
base frequency2,399.99 MHz (2.4 GHz, 2,399,990 kHz) +
bus links1 +
bus rate2,500 MT/s (2.5 GT/s, 2,500,000 kT/s) +
bus typeDMI 1.0 +
chipsetIbex Peak +
clock multiplier18 +
core count2 +
core family6 +
core model37 +
core nameArrandale +
core steppingK0 + and C2 +
cpuid0x20655 +
designerIntel +
device id0x0046 +
die area81 mm² (0.126 in², 0.81 cm², 81,000,000 µm²) +
familyCore i5 +
first announcedJanuary 7, 2010 +
first launchedJanuary 7, 2010 +
full page nameintel/core i5/i5-520m +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 1.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Flex Memory Access +
has intel enhanced speedstep technologytrue +
has intel flex memory access supporttrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 1 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpuHD Graphics (Ironlake) +
integrated gpu base frequency500 MHz (0.5 GHz, 500,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units12 +
integrated gpu max frequency766 MHz (0.766 GHz, 766,000 KHz) +
isax86-64 +
isa familyx86 +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description12-way set associative +
l3$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
last orderOctober 19, 2012 +
last shipmentJanuary 18, 2013 +
ldateJanuary 7, 2010 +
manufacturerIntel +
market segmentMobile + and Embedded +
max cpu count1 +
max junction temperature378.15 K (105 °C, 221 °F, 680.67 °R) +
max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max memory bandwidth15.88 GiB/s (16,261.12 MiB/s, 17.051 GB/s, 17,051.02 MB/s, 0.0155 TiB/s, 0.0171 TB/s) +
max memory channels2 +
max pcie lanes16 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureWestmere +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberi5-520M +
nameIntel Core i5-520M +
packagerPGA-988A + and BGA-1288 +
part numberBX80617I5520M +, CP80617004119AE + and CN80617004119AE +
platformCalpella +
process32 nm (0.032 μm, 3.2e-5 mm) +
release price$ 225.00 (€ 202.50, £ 182.25, ¥ 23,249.25) +
s-specSLBNB +, SLBNA +, SLBU3 + and SLBU4 +
seriesi5-500 +
smp max ways1 +
supported memory typeDDR3-1280 +
tdp35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
technologyCMOS +
thread count4 +
transistor count382,000,000 +
turbo frequency (1 core)2,933.33 MHz (2.933 GHz, 2,933,330 kHz) +
turbo frequency (2 cores)2,666.66 MHz (2.667 GHz, 2,666,660 kHz) +
word size64 bit (8 octets, 16 nibbles) +