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{{amd title|Athlon MP 2100+}} | {{amd title|Athlon MP 2100+}} | ||
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| name = AMD Athlon MP 2100+ | | name = AMD Athlon MP 2100+ | ||
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| max memory = 4 GiB | | max memory = 4 GiB | ||
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| v core = 1.75 V | | v core = 1.75 V | ||
| v core tolerance = | | v core tolerance = | ||
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| tstorage max = 100 °C | | tstorage max = 100 °C | ||
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The '''Athlon MP 2100+''' (OPN ''AMP2100DMS3C'') based on the {{amd|Palomino|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in mid-[[2002]] for the server and workstation market. This MPU operated at 1.73 GHz with a FSB transfer rate of 266 MT/s (x13 multiplier). This processor, which was based on the {{amd|K7|K7 microarchitecture|l=arch}}, was manufactured on a mature [[180 nm]] copper interconnect technology at AMD's Fab 30 in Dresden, Germany. | The '''Athlon MP 2100+''' (OPN ''AMP2100DMS3C'') based on the {{amd|Palomino|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in mid-[[2002]] for the server and workstation market. This MPU operated at 1.73 GHz with a FSB transfer rate of 266 MT/s (x13 multiplier). This processor, which was based on the {{amd|K7|K7 microarchitecture|l=arch}}, was manufactured on a mature [[180 nm]] copper interconnect technology at AMD's Fab 30 in Dresden, Germany. | ||
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== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | {{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | ||
− | {{cache | + | {{cache size |
+ | |l1 cache=128 KiB | ||
|l1i cache=64 KiB | |l1i cache=64 KiB | ||
|l1i break=1x64 KiB | |l1i break=1x64 KiB | ||
|l1i desc=2-way set associative | |l1i desc=2-way set associative | ||
− | |l1i | + | |l1i policy= |
|l1d cache=64 KiB | |l1d cache=64 KiB | ||
|l1d break=1x64 KiB | |l1d break=1x64 KiB | ||
|l1d desc=2-way set associative | |l1d desc=2-way set associative | ||
− | |l1d | + | |l1d policy= |
|l2 cache=256 KiB | |l2 cache=256 KiB | ||
|l2 break=1x256 KiB | |l2 break=1x256 KiB | ||
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
− | |l2 | + | |l2 policy= |
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}} | }} | ||
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|avx=No | |avx=No | ||
|avx2=No | |avx2=No | ||
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|abm=No | |abm=No | ||
|tbm=No | |tbm=No |
Latest revision as of 15:20, 13 December 2017
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AMD Athlon MP 2100+ | |||||||||||
General Info | |||||||||||
Designer | AMD | ||||||||||
Manufacturer | AMD | ||||||||||
Model Number | Athlon MP 2100+ | ||||||||||
Part Number | AMP2100DMS3C | ||||||||||
Market | Server | ||||||||||
Introduction | June 19, 2002 (announced) June 19, 2002 (launched) | ||||||||||
Release Price | $262 | ||||||||||
Shop | Amazon | ||||||||||
General Specs | |||||||||||
Family | Athlon MP | ||||||||||
Locked | Yes | ||||||||||
Frequency | 1,733 MHz | ||||||||||
Bus type | FSB | ||||||||||
Bus speed | 133 MHz | ||||||||||
Bus rate | 266 MT/s | ||||||||||
Clock multiplier | 13 | ||||||||||
CPUID | 662 | ||||||||||
Microarchitecture | |||||||||||
Microarchitecture | K7 | ||||||||||
Platform | Athlon MP | ||||||||||
Chipset | AMD-760MP | ||||||||||
Core Name | Palomino | ||||||||||
Core Family | 6 | ||||||||||
Core Model | 6 | ||||||||||
Core Stepping | 2 | ||||||||||
Process | 180 nm | ||||||||||
Transistors | 37,500,000 | ||||||||||
Technology | CMOS | ||||||||||
Die | 128 mm² | ||||||||||
Word Size | 32 bit | ||||||||||
Cores | 1 | ||||||||||
Threads | 1 | ||||||||||
Max Memory | 4 GiB | ||||||||||
Multiprocessing | |||||||||||
Max SMP | 2-Way (Multiprocessor) | ||||||||||
Electrical | |||||||||||
Vcore | 1.75 V | ||||||||||
TDP | 66 W | ||||||||||
TDP (Typical) | 58.9 W | ||||||||||
Tjunction | 0 °C – 95 °C | ||||||||||
Tcase | 0 °C – 95 °C | ||||||||||
Tstorage | -40 °C – 100 °C | ||||||||||
Packaging | |||||||||||
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The Athlon MP 2100+ (OPN AMP2100DMS3C) based on the Palomino core was a 32-bit x86 multiprocessor developed by AMD and introduced in mid-2002 for the server and workstation market. This MPU operated at 1.73 GHz with a FSB transfer rate of 266 MT/s (x13 multiplier). This processor, which was based on the K7 microarchitecture, was manufactured on a mature 180 nm copper interconnect technology at AMD's Fab 30 in Dresden, Germany.
Cache[edit]
- Main article: K7 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics[edit]
This MPU has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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- Advanced Configuration and Power Interface
- Halt State
- Stop Grant State
Documents[edit]
Datasheets[edit]
- AMD Athlon MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms; Publication # 25480 Rev: D; Issue Date: June 2002.
Others[edit]
- System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors; Publication # 25325; Rev: B; August 2002.
Facts about "Athlon MP 2100+ - AMD"
has feature | ACPI +, Halt State + and Stop Grant State + |
l1d$ description | 2-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |