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Difference between revisions of "qualcomm/msm6xxx/msm6800"
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{{qualcomm title|MSM6800}}
 
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| name                = Qualcomm MSM6800
 
| name                = Qualcomm MSM6800
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== Digital Signal Processing ==
 
== Digital Signal Processing ==
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* '''DPS:''' 2x [[dps processor::QDSP4000]] [[dps processor base frequency::90 MHz]]
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* '''DSP:''' 2x [[dsp::QDSP4000]] [[dsp base frequency::90 MHz]]
  
 
== Expansions ==
 
== Expansions ==
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{{expand list}}
 
{{expand list}}
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== Diagram ==
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[[File:diagram msm6800.jpg|1000px]]
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== Documents ==
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=== Datasheets ===
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* [[:File:diagram msm6800 cs.pdf|MSM6800 Diagram]]
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* [[:File:msm6800 chipset.pdf|MSM6800 Chipset]]
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* [[:File:MSM6800 chipset sol.pdf|MSM6800 Chipset]]
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=== Other ===
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* [[:File:platform enhanced.pdf|Enhanced Multimedia Platform Overview]]

Latest revision as of 15:32, 13 December 2017

Edit Values
Qualcomm MSM6800
msm6800 lowres.jpg
General Info
DesignerQualcomm,
ARM Holdings
ManufacturerTSMC, IBM
Model NumberMSM6800
MarketMobile, Embedded
IntroductionApril 13, 2005 (announced)
April, 2006 (launched)
General Specs
FamilyMSM6xxx
SeriesMSM
LockedYes
Frequency270 MHz
Bus typeAMBA 2
Microarchitecture
MicroarchitectureARM9
ChipsetMSM6xxx
Core NameARM926EJ-S
Process130 nm, 90 nm
TechnologyCMOS
Cores1
Threads1
Max Memory4 GiB
Max Address Mem0xFFFFFFFF
Multiprocessing
Max SMP1-Way (Uniprocessor)

MSM6800 is a 32-bit ARM system-on-chip with 3G wireless capabilities developed by Qualcomm and introduced in 2006 for the mobile market. This SoC was part of the MSM6xxx Enhanced Multimedia Platform offering support for the most advanced features such as security, position-location, camera & imaging, audio, video, streaming, and conferencing.

Cache[edit]

Main article: ARM9 § Cache
Cache Info [Edit Values]
L1I$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 4-way set associative
L1D$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 4-way set associative

Wireless[edit]

Antu network-wireless-connected-100.svgWireless Communications
Cellular
2G
GSM Yes
GPRS Yes
cdmaOne
IS-95AYes
IS-95BYes
3G
CDMA2000
1XYes
1xEV-DOYes

Digital Signal Processing[edit]

  • DSP: 2x QDSP4000 90 MHz
    0.09 GHz
    90,000 kHz

Expansions[edit]

  • LCD: 24bpp, WQVGA
  • USB: USB 2.0 FS Slave and Host
  • Camera: up to 5 megapixel
  • Bluetooth: BT 1.2
  • Video Codecs: MPEG-4, H.263, H.264, Windows Media and RealNetworks
  • Audio Codecs: AMR-NB, AMR-WB/+, AAC, aacPlusTM and Enhanced aacPlus, Windows Media and RealNetworks
  • gpsOne position-location capabilities
  • Support for digital stereo output up to 48 kHz
  • MIDI Synthesizer (72 polyphony)
  • Hardware-based Image Signal Processor and JPEG encoder

Utilizing devices[edit]

This list is incomplete; you can help by expanding it.

Diagram[edit]

diagram msm6800.jpg

Documents[edit]

Datasheets[edit]

Other[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=qualcomm/msm6xxx/msm6800&oldid=71188"
Facts about "MSM6800 - Qualcomm"
RDF feed
base frequency270 MHz (0.27 GHz, 270,000 kHz) +
bus typeAMBA 2 +
chipsetMSM6xxx +
core count1 +
core nameARM926EJ-S +
designerQualcomm + and ARM Holdings +
dspQDSP4000 +
dsp base frequency90 MHz (0.09 GHz, 90,000 kHz) +
familyMSM6xxx +
first announcedApril 13, 2005 +
first launchedApril 2006 +
full page namequalcomm/msm6xxx/msm6800 +
has 2g supporttrue +
has 3g supporttrue +
has cdma2000 1x supporttrue +
has cdma2000 1xev-do supporttrue +
has cdma2000 supporttrue +
has cdmaone supporttrue +
has gprs supporttrue +
has gsm supporttrue +
has is-95a supporttrue +
has is-95b supporttrue +
has locked clock multipliertrue +
instance ofmicroprocessor +
l1d$ description4-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
ldateApril 2006 +
main imageFile:msm6800 lowres.jpg +
manufacturerTSMC + and IBM +
market segmentMobile + and Embedded +
max cpu count1 +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory address0xFFFFFFFF +
microarchitectureARM9 +
model numberMSM6800 +
nameQualcomm MSM6800 +
part ofEnhanced Multimedia Platform +
process130 nm (0.13 μm, 1.3e-4 mm) + and 90 nm (0.09 μm, 9.0e-5 mm) +
seriesMSM +
smp max ways1 +
technologyCMOS +
thread count1 +