From WikiChip
Difference between revisions of "intel/xeon e5/e5-2687w v4"
(+q-spec) |
m (Bot: moving all {{mpu}} to {{chip}}) |
||
(10 intermediate revisions by 4 users not shown) | |||
Line 1: | Line 1: | ||
{{intel title|Xeon E5-2687W v4}} | {{intel title|Xeon E5-2687W v4}} | ||
− | {{ | + | {{chip |
− | | name | + | |name=Xeon E5-2687W v4 |
− | | no image | + | |no image=Yes |
− | + | |designer=Intel | |
− | + | |manufacturer=Intel | |
− | + | |model number=E5-2687W v4 | |
− | | designer | + | |part number=CM8066002042802 |
− | | manufacturer | + | |part number 2=BX80660E52687V4 |
− | | model number | + | |s-spec=SR2NA |
− | | part number | + | |s-spec qs=QK99 |
− | | part number | + | |market=Server |
− | | | + | |first announced=June 20, 2016 |
− | | | + | |first launched=June 20, 2016 |
− | | market | + | |release price=$2141.00 |
− | | first announced | + | |family=Xeon E5 |
− | | first launched | + | |series=E5-2600 |
− | + | |locked=Yes | |
− | + | |frequency=3,000 MHz | |
− | | release price | + | |turbo frequency1=3,500 MHz |
− | + | |turbo frequency2=3,500 MHz | |
− | | family | + | |turbo frequency3=3,300 MHz |
− | | series | + | |turbo frequency4=3,200 MHz |
− | | locked | + | |turbo frequency5=3,200 MHz |
− | | frequency | + | |turbo frequency6=3,200 MHz |
− | | turbo | + | |turbo frequency7=3,200 MHz |
− | | turbo | + | |turbo frequency8=3,200 MHz |
− | | turbo | + | |turbo frequency9=3,200 MHz |
− | | bus type | + | |turbo frequency10=3,200 MHz |
− | | bus speed | + | |turbo frequency11=3,200 MHz |
− | | bus rate | + | |turbo frequency12=3,200 MHz |
− | + | |bus type=QPI | |
− | | clock multiplier | + | |bus speed=4,800 MHz |
− | | | + | |bus links=2 |
− | | | + | |bus rate=9.6 GT/s |
− | + | |clock multiplier=30 | |
− | | | + | |cpuid=406F1 |
− | + | |isa=x86-64 | |
− | | microarch | + | |isa family=x86 |
− | | platform | + | |microarch=Broadwell |
− | | chipset | + | |platform=Grantley EP 2S |
− | | core name | + | |chipset=C610 Series |
− | | core family | + | |core name=Broadwell EP |
− | | core model | + | |core family=6 |
− | | core stepping | + | |core model=4F |
− | | process | + | |core stepping=M0 |
− | | transistors | + | |process=14 nm |
− | | technology | + | |transistors=4,700,000,000 |
− | + | |technology=CMOS | |
− | | word size | + | |word size=64 bit |
− | | core count | + | |core count=12 |
− | | thread count | + | |thread count=24 |
− | | max cpus | + | |max cpus=2 |
− | | max memory | + | |max memory=1,536 GiB |
− | + | |v core=1.82 V | |
− | + | |v io=1.2 V | |
− | | v core | + | |v io tolerance=3% |
− | + | |tdp=160 W | |
− | | v io | + | |tcase min=0 °C |
− | | v io tolerance | + | |tcase max=76 °C |
− | + | |tstorage min=-25 °C | |
− | | tdp | + | |tstorage max=125 °C |
− | + | |turbo frequency=Yes | |
− | + | |die size=306.18 mm² | |
− | + | |packaging=Yes | |
− | + | |package 0=FCLGA-2011-v3 | |
− | + | |package 0 type=FCLGA | |
− | + | |package 0 pins=2011 | |
− | | tcase min | + | |package 0 pitch=0.8814 mm |
− | | tcase max | + | |package 0 width=52.5 mm |
− | | tstorage min | + | |package 0 length=45.0 mm |
− | | tstorage max | + | |package 0 height=5.316 mm |
− | + | |socket 0=LGA-2011-v3 | |
− | | packaging | + | |socket 0 type=LGA |
− | | package 0 | ||
− | | package 0 type | ||
− | | package 0 pins | ||
− | | package 0 pitch | ||
− | | package 0 width | ||
− | | package 0 length | ||
− | | package 0 height | ||
− | | socket 0 | ||
− | | socket 0 type | ||
}} | }} | ||
The '''Xeon E5-2687W v4''' is a {{arch|64}} [[dodeca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for 2S workstation environments. Operating at 3 GHz with a {{intel|turbo boost}} frequency of 3.5 GHz for a single active core, this MPU has a TDP of 160 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}). | The '''Xeon E5-2687W v4''' is a {{arch|64}} [[dodeca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for 2S workstation environments. Operating at 3 GHz with a {{intel|turbo boost}} frequency of 3.5 GHz for a single active core, this MPU has a TDP of 160 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}). | ||
Line 123: | Line 114: | ||
== Expansions == | == Expansions == | ||
− | {{ | + | {{expansions |
| pcie revision = 3.0 | | pcie revision = 3.0 | ||
| pcie lanes = 40 | | pcie lanes = 40 | ||
Line 132: | Line 123: | ||
== Features == | == Features == | ||
− | {{ | + | {{x86 features |
| em64t = Yes | | em64t = Yes | ||
| nx = Yes | | nx = Yes | ||
Line 154: | Line 145: | ||
| sse4.2 = Yes | | sse4.2 = Yes | ||
| aes = Yes | | aes = Yes | ||
− | | pclmul | + | | pclmul = Yes |
| avx = Yes | | avx = Yes | ||
| avx2 = Yes | | avx2 = Yes |
Latest revision as of 15:28, 13 December 2017
Edit Values | |
Xeon E5-2687W v4 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | E5-2687W v4 |
Part Number | CM8066002042802, BX80660E52687V4 |
S-Spec | SR2NA QK99 (QS) |
Market | Server |
Introduction | June 20, 2016 (announced) June 20, 2016 (launched) |
Release Price | $2141.00 |
Shop | Amazon |
General Specs | |
Family | Xeon E5 |
Series | E5-2600 |
Locked | Yes |
Frequency | 3,000 MHz |
Turbo Frequency | Yes |
Turbo Frequency | 3,500 MHz (1 core), 3,500 MHz (2 cores), 3,300 MHz (3 cores), 3,200 MHz (4 cores), 3,200 MHz (5 cores), 3,200 MHz (6 cores), 3,200 MHz (7 cores), 3,200 MHz (8 cores), 3,200 MHz (9 cores), 3,200 MHz (10 cores), 3,200 MHz (11 cores), 3,200 MHz (12 cores) |
Bus type | QPI |
Bus speed | 4,800 MHz |
Bus rate | 2 × 9.6 GT/s |
Clock multiplier | 30 |
CPUID | 406F1 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Broadwell |
Platform | Grantley EP 2S |
Chipset | C610 Series |
Core Name | Broadwell EP |
Core Family | 6 |
Core Model | 4F |
Core Stepping | M0 |
Process | 14 nm |
Transistors | 4,700,000,000 |
Technology | CMOS |
Die | 306.18 mm² |
Word Size | 64 bit |
Cores | 12 |
Threads | 24 |
Max Memory | 1,536 GiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
Vcore | 1.82 V |
VI/O | 1.2 V ± 3% |
TDP | 160 W |
Tcase | 0 °C – 76 °C |
Tstorage | -25 °C – 125 °C |
The Xeon E5-2687W v4 is a 64-bit dodeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for 2S workstation environments. Operating at 3 GHz with a turbo boost frequency of 3.5 GHz for a single active core, this MPU has a TDP of 160 W and is manufactured on a 14 nm process (based on Broadwell).
Cache[edit]
- Main article: Broadwell § Cache
Cache Info [Edit Values] | ||
L1I$ | 384 KiB 393,216 B 0.375 MiB |
12x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 384 KiB 393,216 B 0.375 MiB |
12x32 KiB 8-way set associative (per core, write-back) |
L2$ | 3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB |
12x256 KiB 8-way set associative (per core, write-back) |
L3$ | 30 MiB 30,720 KiB 31,457,280 B 0.0293 GiB |
12x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics[edit]
This microprocessor has no integrated graphics processing unit.
Memory controller[edit]
Integrated Memory Controller | |
Type | DDR4-2400 |
Controllers | 1 |
Channels | 4 |
ECC Support | Yes |
Max bandwidth | 71.53 GiB/s |
Bandwidth (single) | 17.88 GiB/s |
Bandwidth (dual) | 35.76 GiB/s |
Max memory | 1,536 GiB |
Physical Address Extensions | 46 bit |
Expansions[edit]
Expansion Options
|
||||||||
|
Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
||||||||||||||||||||||||||||||||||||||||
|
Facts about "Xeon E5-2687W v4 - Intel"
l1d$ description | 8-way set associative + |
l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 30 MiB (30,720 KiB, 31,457,280 B, 0.0293 GiB) + |