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Difference between revisions of "intel/xeon e5/e5-2609 v4"
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{{intel title|Xeon E5-2609 v4}} | {{intel title|Xeon E5-2609 v4}} | ||
− | {{ | + | {{chip |
| name = Xeon E5-2609 v4 | | name = Xeon E5-2609 v4 | ||
| no image = Yes | | no image = Yes | ||
Line 10: | Line 10: | ||
| model number = E5-2609 v4 | | model number = E5-2609 v4 | ||
| part number = CM8066002032901 | | part number = CM8066002032901 | ||
− | | part number | + | | part number 2 = BX80660E52609V4 |
− | |||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Server | | market = Server | ||
| first announced = June 20, 2016 | | first announced = June 20, 2016 | ||
Line 29: | Line 29: | ||
| bus links = 2 | | bus links = 2 | ||
| clock multiplier = 17 | | clock multiplier = 17 | ||
− | | s-spec = | + | | s-spec = SR2P1 |
| s-spec es = | | s-spec es = | ||
− | | s-spec qs = | + | | s-spec qs = QKEW |
| cpuid = 406F1 | | cpuid = 406F1 | ||
+ | | isa family = x86 | ||
+ | | isa = x86-64 | ||
| microarch = Broadwell | | microarch = Broadwell | ||
| platform = Grantley EP 2S | | platform = Grantley EP 2S | ||
Line 51: | Line 53: | ||
| max memory = 1,536 GiB | | max memory = 1,536 GiB | ||
− | + | ||
| v core = 1.82 V | | v core = 1.82 V | ||
| v core tolerance = | | v core tolerance = | ||
Line 80: | Line 82: | ||
| socket 0 type = LGA | | socket 0 type = LGA | ||
}} | }} | ||
− | The '''Xeon E5-2609 v4''' is a {{arch|64}} [[octa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for basic 2S environments (1U square form factor). Operating at 1.7 GHz with a {{intel|turbo boost}} frequency of 3.2 GHz for a single active core, this MPU has a TDP of 85 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}). | + | The '''Xeon E5-2609 v4''' is a {{arch|64}} [[octa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for basic 2S environments (1U square form factor). Operating at 1.7 GHz with a {{intel|turbo boost}} frequency of 3.2 GHz for a single active core, this MPU has a TDP of 85 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}). This specific model has no hyper-threading support. |
== Cache == | == Cache == | ||
Line 117: | Line 119: | ||
| max memory = 1,536 GiB | | max memory = 1,536 GiB | ||
| pae = 46 bit | | pae = 46 bit | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 40 | ||
+ | | pcie config = x4 | ||
+ | | pcie config 1 = x8 | ||
+ | | pcie config 2 = x16 | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | | em64t = Yes | ||
+ | | nx = Yes | ||
+ | | txt = Yes | ||
+ | | tsx = Yes | ||
+ | | vpro = Yes | ||
+ | | ht = | ||
+ | | tbt1 = | ||
+ | | tbt2 = | ||
+ | | tbmt3 = | ||
+ | | bpt = | ||
+ | | vt-x = Yes | ||
+ | | vt-d = Yes | ||
+ | | ept = Yes | ||
+ | | mmx = Yes | ||
+ | | sse = Yes | ||
+ | | sse2 = Yes | ||
+ | | sse3 = Yes | ||
+ | | ssse3 = Yes | ||
+ | | sse4.1 = Yes | ||
+ | | sse4.2 = Yes | ||
+ | | aes = Yes | ||
+ | | pclmul = Yes | ||
+ | | avx = Yes | ||
+ | | avx2 = Yes | ||
+ | | bmi = Yes | ||
+ | | bmi1 = Yes | ||
+ | | bmi2 = Yes | ||
+ | | f16c = Yes | ||
+ | | fma3 = Yes | ||
+ | | mpx = | ||
+ | | sgx = | ||
+ | | eist = Yes | ||
+ | | secure key = Yes | ||
+ | | os guard = Yes | ||
+ | | intel at = | ||
+ | | intel ipt = | ||
}} | }} |
Latest revision as of 15:27, 13 December 2017
Edit Values | |
Xeon E5-2609 v4 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | E5-2609 v4 |
Part Number | CM8066002032901, BX80660E52609V4 |
S-Spec | SR2P1 QKEW (QS) |
Market | Server |
Introduction | June 20, 2016 (announced) June 20, 2016 (launched) |
Release Price | $306.00 |
Shop | Amazon |
General Specs | |
Family | Xeon E5 |
Series | E5-2000 |
Locked | Yes |
Frequency | 1,700 MHz |
Bus type | QPI |
Bus speed | 3,200 MHz |
Bus rate | 2 × 6.4 GT/s |
Clock multiplier | 17 |
CPUID | 406F1 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Broadwell |
Platform | Grantley EP 2S |
Chipset | C610 Series |
Core Name | Broadwell EP |
Core Family | 6 |
Core Model | 4F |
Core Stepping | R0 |
Process | 14 nm |
Transistors | 3,200,000,000 |
Technology | CMOS |
Die | 246.24 mm² |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Max Memory | 1,536 GiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
Vcore | 1.82 V |
VI/O | 1.2 V ± 3% |
TDP | 85 W |
Tcase | 0 °C – 74 °C |
Tstorage | -25 °C – 125 °C |
The Xeon E5-2609 v4 is a 64-bit octa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for basic 2S environments (1U square form factor). Operating at 1.7 GHz with a turbo boost frequency of 3.2 GHz for a single active core, this MPU has a TDP of 85 W and is manufactured on a 14 nm process (based on Broadwell). This specific model has no hyper-threading support.
Cache[edit]
- Main article: Broadwell § Cache
Cache Info [Edit Values] | ||
L1I$ | 256 KiB 262,144 B 0.25 MiB |
8x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 256 KiB 262,144 B 0.25 MiB |
8x32 KiB 8-way set associative (per core, write-back) |
L2$ | 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB |
8x256 KiB 8-way set associative (per core, write-back) |
L3$ | 20 MiB 20,480 KiB 20,971,520 B 0.0195 GiB |
8x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics[edit]
This microprocessor has no integrated graphics processing unit.
Memory controller[edit]
Integrated Memory Controller | |
Type | DDR4-1866 |
Controllers | 1 |
Channels | 4 |
ECC Support | Yes |
Max bandwidth | 55.63 GiB/s |
Bandwidth (single) | 13.91 GiB/s |
Bandwidth (dual) | 27.82 GiB/s |
Max memory | 1,536 GiB |
Physical Address Extensions | 46 bit |
Expansions[edit]
Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Facts about "Xeon E5-2609 v4 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E5-2609 v4 - Intel#io + |
base frequency | 1,700 MHz (1.7 GHz, 1,700,000 kHz) + |
bus links | 2 + |
bus rate | 6,400 MT/s (6.4 GT/s, 6,400,000 kT/s) + |
bus speed | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
bus type | QPI + |
chipset | C610 Series + |
clock multiplier | 17 + |
core count | 8 + |
core family | 6 + |
core model | 4F + |
core name | Broadwell EP + |
core stepping | R0 + |
core voltage | 1.82 V (18.2 dV, 182 cV, 1,820 mV) + |
cpuid | 406F1 + |
designer | Intel + |
die area | 246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) + |
family | Xeon E5 + |
first announced | June 20, 2016 + |
first launched | June 20, 2016 + |
full page name | intel/xeon e5/e5-2609 v4 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has extended page tables support | true + |
has feature | Trusted Execution Technology +, Transactional Synchronization Extensions +, Intel vPro Technology +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology + and Extended Page Tables + |
has intel enhanced speedstep technology | true + |
has intel trusted execution technology | true + |
has intel vpro technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
io voltage | 1.2 V (12 dV, 120 cV, 1,200 mV) + |
io voltage tolerance | 3% + |
isa | x86-64 + |
isa family | x86 + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) + |
ldate | June 20, 2016 + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 347.15 K (74 °C, 165.2 °F, 624.87 °R) + |
max cpu count | 2 + |
max memory | 1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) + |
max pcie lanes | 40 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Broadwell + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | E5-2609 v4 + |
name | Xeon E5-2609 v4 + |
part number | CM8066002032901 + and BX80660E52609V4 + |
platform | Grantley EP 2S + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 306.00 (€ 275.40, £ 247.86, ¥ 31,618.98) + |
s-spec | SR2P1 + |
s-spec (qs) | QKEW + |
series | E5-2000 + |
smp max ways | 2 + |
tdp | 85 W (85,000 mW, 0.114 hp, 0.085 kW) + |
technology | CMOS + |
thread count | 8 + |
transistor count | 3,200,000,000 + |
word size | 64 bit (8 octets, 16 nibbles) + |