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Difference between revisions of "intel/xeon e5/e5-2667 v4"
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{{intel title|Xeon E5-2667 v4}}
 
{{intel title|Xeon E5-2667 v4}}
−
{{mpu
+
{{chip
 
| name                = Xeon E5-2667 v4
 
| name                = Xeon E5-2667 v4
 
| no image            = Yes
 
| no image            = Yes
Line 10: Line 10:
 
| model number        = E5-2667 v4
 
| model number        = E5-2667 v4
 
| part number        = CM8066002041900
 
| part number        = CM8066002041900
−
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Server
 
| market              = Server
 
| first announced    = June 20, 2016
 
| first announced    = June 20, 2016
Line 26: Line 26:
 
| turbo frequency    = Yes
 
| turbo frequency    = Yes
 
| turbo frequency1    = 3,600 MHz
 
| turbo frequency1    = 3,600 MHz
−
| turbo frequency2    =  
+
| turbo frequency2    = 3,600 MHz
 +
| turbo frequency3    = 3,500 MHz
 +
| turbo frequency4    = 3,500 MHz
 +
| turbo frequency5    = 3,500 MHz
 +
| turbo frequency6    = 3,500 MHz
 +
| turbo frequency7    = 3,500 MHz
 +
| turbo frequency8    = 3,500 MHz
 
| bus type            = QPI
 
| bus type            = QPI
 
| bus speed          = 4,800 MHz
 
| bus speed          = 4,800 MHz
Line 34: Line 40:
 
| s-spec              = SR2P5
 
| s-spec              = SR2P5
 
| s-spec es          =  
 
| s-spec es          =  
−
| s-spec qs          =  
+
| s-spec qs          = QKF0
 
| cpuid              = 406F1
 
| cpuid              = 406F1
  
 +
| isa family          = x86
 +
| isa                = x86-64
 
| microarch          = Broadwell
 
| microarch          = Broadwell
 
| platform            = Grantley EP 2S
 
| platform            = Grantley EP 2S
Line 54: Line 62:
 
| max memory          = 1,536 GiB
 
| max memory          = 1,536 GiB
  
−
| electrical          = Yes
+
 
 
| v core              = 1.82 V
 
| v core              = 1.82 V
 
| v core tolerance    =  
 
| v core tolerance    =  
Line 96: Line 104:
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d extra=(per core, write-back)
 
|l1d extra=(per core, write-back)
−
|l2 cache=4 MiB
+
|l2 cache=2 MiB
 
|l2 break=8x256 KiB
 
|l2 break=8x256 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l2 extra=(per core, write-back)
 
|l2 extra=(per core, write-back)
 
|l3 cache=25 MiB
 
|l3 cache=25 MiB
−
|l3 break=8x3.125 MiB
+
|l3 break=10x2.5 MiB
 
|l3 desc=20-way set associative
 
|l3 desc=20-way set associative
 
|l3 extra=(shared, per core, write-back)
 
|l3 extra=(shared, per core, write-back)
 +
}}
 +
 +
== Graphics ==
 +
This microprocessor has no [[integrated graphics processing unit]].
 +
 +
== Memory controller ==
 +
{{integrated memory controller
 +
| type              = DDR4-2400
 +
| controllers        = 1
 +
| channels          = 4
 +
| ecc support        = Yes
 +
| max bandwidth      = 71.53 GiB/s
 +
| bandwidth schan    = 17.88 GiB/s
 +
| bandwidth dchan    = 35.76 GiB/s
 +
| max memory        = 1,536 GiB
 +
| pae                = 46 bit
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 40
 +
| pcie config        = x4
 +
| pcie config 1      = x8
 +
| pcie config 2      = x16
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
| em64t      = Yes
 +
| nx          = Yes
 +
| txt        = Yes
 +
| tsx        = Yes
 +
| vpro        = Yes
 +
| ht          = Yes
 +
| tbt1        =
 +
| tbt2        = Yes
 +
| tbmt3      =
 +
| bpt        =
 +
| vt-x        = Yes
 +
| vt-d        = Yes
 +
| ept        = Yes
 +
| mmx        = Yes
 +
| sse        = Yes
 +
| sse2        = Yes
 +
| sse3        = Yes
 +
| ssse3      = Yes
 +
| sse4.1      = Yes
 +
| sse4.2      = Yes
 +
| aes        = Yes
 +
| pclmul      = Yes
 +
| avx        = Yes
 +
| avx2        = Yes
 +
| bmi        = Yes
 +
| bmi1        = Yes
 +
| bmi2        = Yes
 +
| f16c        = Yes
 +
| fma3        = Yes
 +
| mpx        =
 +
| sgx        =
 +
| eist        = Yes
 +
| secure key  = Yes
 +
| os guard    = Yes
 +
| intel at    =
 +
| intel ipt  =
 
}}
 
}}

Latest revision as of 11:13, 1 August 2019

Edit Values
Xeon E5-2667 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-2667 v4
Part NumberCM8066002041900
S-SpecSR2P5
QKF0 (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$2057.00
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-2000
LockedYes
Frequency3,200 MHz
Turbo FrequencyYes
Turbo Frequency3,600 MHz (1 core),
3,600 MHz (2 cores),
3,500 MHz (3 cores),
3,500 MHz (4 cores),
3,500 MHz (5 cores),
3,500 MHz (6 cores),
3,500 MHz (7 cores),
3,500 MHz (8 cores)
Bus typeQPI
Bus speed4,800 MHz
Bus rate2 × 9.6 GT/s
Clock multiplier32
CPUID406F1
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureBroadwell
PlatformGrantley EP 2S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingR0
Process14 nm
Transistors3,200,000,000
TechnologyCMOS
Die246.24 mm²
Word Size64 bit
Cores8
Threads16
Max Memory1,536 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP135 W
Tcase0 °C – 78 °C
Tstorage-25 °C – 125 °C

The Xeon E5-2667 v4 is a 64-bit octa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for frequency-optimized 2S environments (2U square form factor). Operating at 3.2 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core, write-back)
L1D$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core, write-back)
L2$ 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
8x256 KiB 8-way set associative (per core, write-back)
L3$ 25 MiB
25,600 KiB
26,214,400 B
0.0244 GiB
10x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

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Facts about "Xeon E5-2667 v4 - Intel"
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Xeon E5-2667 v4 - Intel#io +
base frequency3,200 MHz (3.2 GHz, 3,200,000 kHz) +
bus links2 +
bus rate9,600 MT/s (9.6 GT/s, 9,600,000 kT/s) +
bus speed4,800 MHz (4.8 GHz, 4,800,000 kHz) +
bus typeQPI +
chipsetC610 Series +
clock multiplier32 +
core count8 +
core family6 +
core model4F +
core nameBroadwell EP +
core steppingR0 +
core voltage1.82 V (18.2 dV, 182 cV, 1,820 mV) +
cpuid406F1 +
designerIntel +
die area246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) +
familyXeon E5 +
first announcedJune 20, 2016 +
first launchedJune 20, 2016 +
full page nameintel/xeon e5/e5-2667 v4 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
io voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
io voltage tolerance3% +
isax86-64 +
isa familyx86 +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ description20-way set associative +
l3$ size25 MiB (25,600 KiB, 26,214,400 B, 0.0244 GiB) +
ldateJune 20, 2016 +
manufacturerIntel +
market segmentServer +
max case temperature351.15 K (78 °C, 172.4 °F, 632.07 °R) +
max cpu count2 +
max memory1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max pcie lanes40 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureBroadwell +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberE5-2667 v4 +
nameXeon E5-2667 v4 +
part numberCM8066002041900 +
platformGrantley EP 2S +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 2,057.00 (€ 1,851.30, £ 1,666.17, ¥ 212,549.81) +
s-specSR2P5 +
s-spec (qs)QKF0 +
seriesE5-2000 +
smp max ways2 +
tdp135 W (135,000 mW, 0.181 hp, 0.135 kW) +
technologyCMOS +
thread count16 +
transistor count3,200,000,000 +
turbo frequency (1 core)3,600 MHz (3.6 GHz, 3,600,000 kHz) +
turbo frequency (2 cores)3,600 MHz (3.6 GHz, 3,600,000 kHz) +
turbo frequency (3 cores)3,500 MHz (3.5 GHz, 3,500,000 kHz) +
turbo frequency (4 cores)3,500 MHz (3.5 GHz, 3,500,000 kHz) +
turbo frequency (5 cores)3,500 MHz (3.5 GHz, 3,500,000 kHz) +
turbo frequency (6 cores)3,500 MHz (3.5 GHz, 3,500,000 kHz) +
turbo frequency (7 cores)3,500 MHz (3.5 GHz, 3,500,000 kHz) +
turbo frequency (8 cores)3,500 MHz (3.5 GHz, 3,500,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +