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{{intel title|Xeon E5-4610 v4}}
 
{{intel title|Xeon E5-4610 v4}}
−
{{mpu
+
{{chip
 
| name                = Xeon E5-4610 v4
 
| name                = Xeon E5-4610 v4
 
| no image            = Yes
 
| no image            = Yes
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| model number        = E5-4610 v4
 
| model number        = E5-4610 v4
 
| part number        = CM8066002062800
 
| part number        = CM8066002062800
−
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Server
 
| market              = Server
 
| first announced    = June 20, 2016
 
| first announced    = June 20, 2016
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| s-spec              = SR2SE
 
| s-spec              = SR2SE
 
| s-spec es          =  
 
| s-spec es          =  
−
| s-spec qs          =  
+
| s-spec qs          = QKSU
 
| cpuid              = 406F1
 
| cpuid              = 406F1
  
 +
| isa family          = x86
 +
| isa                = x86-64
 
| microarch          = Broadwell
 
| microarch          = Broadwell
 
| platform            = Grantley EP 4S
 
| platform            = Grantley EP 4S
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| max memory          = 1,536 GiB
 
| max memory          = 1,536 GiB
  
−
| electrical          = Yes
+
 
 
| v core              = 1.82 V
 
| v core              = 1.82 V
 
| v core tolerance    =  
 
| v core tolerance    =  
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}}
 
}}
 
The '''Xeon E5-4610 v4''' is a {{arch|64}} [[deca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for basic 4S environments. Operating at base frequency of 1.8 GHz with no {{intel|turbo boost}}, this MPU has a TDP of 105 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 
The '''Xeon E5-4610 v4''' is a {{arch|64}} [[deca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for basic 4S environments. Operating at base frequency of 1.8 GHz with no {{intel|turbo boost}}, this MPU has a TDP of 105 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
 +
{{cache info
 +
|l1i cache=320 KiB
 +
|l1i break=10x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i extra=(per core, write-back)
 +
|l1d cache=320 KiB
 +
|l1d break=10x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d extra=(per core, write-back)
 +
|l2 cache=2.5 MiB
 +
|l2 break=10x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 extra=(per core, write-back)
 +
|l3 cache=25 MiB
 +
|l3 break=10x2.5 MiB
 +
|l3 desc=20-way set associative
 +
|l3 extra=(shared, per core, write-back)
 +
}}
 +
 +
== Graphics ==
 +
This microprocessor has no [[integrated graphics processing unit]].
 +
 +
== Memory controller ==
 +
{{integrated memory controller
 +
| type              = DDR4-2133
 +
| controllers        = 1
 +
| channels          = 4
 +
| ecc support        = Yes
 +
| max bandwidth      = 63.58 GiB/s
 +
| bandwidth schan    = 15.89 GiB/s
 +
| bandwidth dchan    = 31.79 GiB/s
 +
| max memory        = 1,536 GiB
 +
| pae                = 46 bit
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 40
 +
| pcie config        = x4
 +
| pcie config 1      = x8
 +
| pcie config 2      = x16
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
| em64t      = Yes
 +
| nx          = Yes
 +
| txt        = Yes
 +
| tsx        = Yes
 +
| vpro        =
 +
| ht          = Yes
 +
| tbt1        =
 +
| tbt2        =
 +
| tbmt3      =
 +
| bpt        =
 +
| vt-x        = Yes
 +
| vt-d        = Yes
 +
| ept        = Yes
 +
| mmx        = Yes
 +
| sse        = Yes
 +
| sse2        = Yes
 +
| sse3        = Yes
 +
| ssse3      = Yes
 +
| sse4.1      = Yes
 +
| sse4.2      = Yes
 +
| aes        = Yes
 +
| pclmul      = Yes
 +
| avx        = Yes
 +
| avx2        = Yes
 +
| bmi        = Yes
 +
| bmi1        = Yes
 +
| bmi2        = Yes
 +
| f16c        = Yes
 +
| fma3        = Yes
 +
| mpx        =
 +
| sgx        =
 +
| eist        = Yes
 +
| secure key  = Yes
 +
| os guard    = Yes
 +
| intel at    =
 +
| intel ipt  =
 +
}}

Latest revision as of 16:28, 13 December 2017

Edit Values
Xeon E5-4610 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-4610 v4
Part NumberCM8066002062800
S-SpecSR2SE
QKSU (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$1219
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-4000
LockedYes
Frequency1,800 MHz
Bus typeQPI
Bus speed3,200 MHz
Bus rate2 × 6.4 GT/s
Clock multiplier18
CPUID406F1
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureBroadwell
PlatformGrantley EP 4S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingM0
Process14 nm
Transistors3,200,000,000
TechnologyCMOS
Die246.24 mm²
Word Size64 bit
Cores10
Threads20
Max Memory1,536 GiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP105 W
Tcase0 °C – 79 °C
Tstorage-25 °C – 125 °C

The Xeon E5-4610 v4 is a 64-bit deca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for basic 4S environments. Operating at base frequency of 1.8 GHz with no turbo boost, this MPU has a TDP of 105 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 320 KiB
327,680 B
0.313 MiB
10x32 KiB 8-way set associative (per core, write-back)
L1D$ 320 KiB
327,680 B
0.313 MiB
10x32 KiB 8-way set associative (per core, write-back)
L2$ 2.5 MiB
2,560 KiB
2,621,440 B
0.00244 GiB
10x256 KiB 8-way set associative (per core, write-back)
L3$ 25 MiB
25,600 KiB
26,214,400 B
0.0244 GiB
10x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2133
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 63.58 GiB/s
Bandwidth (single) 15.89 GiB/s
Bandwidth (dual) 31.79 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

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Facts about "Xeon E5-4610 v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size320 KiB (327,680 B, 0.313 MiB) +
l1i$ description8-way set associative +
l1i$ size320 KiB (327,680 B, 0.313 MiB) +
l2$ description8-way set associative +
l2$ size2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
l3$ description20-way set associative +
l3$ size25 MiB (25,600 KiB, 26,214,400 B, 0.0244 GiB) +