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Difference between revisions of "amd/duron/dhm0850avs1bm"
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{{amd title|Duron 850 (Camaro)}}
 
{{amd title|Duron 850 (Camaro)}}
−
{{mpu
+
{{chip
 
| name                = Duron 850
 
| name                = Duron 850
 
| no image            = Yes
 
| no image            = Yes
Line 10: Line 10:
 
| model number        = Duron 850
 
| model number        = Duron 850
 
| part number        = DHM0850AVS1BM
 
| part number        = DHM0850AVS1BM
−
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Mobile
 
| market              = Mobile
 
| first announced    = 2001
 
| first announced    = 2001
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| bus speed          = 100 MHz
 
| bus speed          = 100 MHz
 
| bus rate            = 200 MT/s
 
| bus rate            = 200 MT/s
−
| clock multiplier    = 8
+
| clock multiplier    = 8.5
 
| cpuid              = 660
 
| cpuid              = 660
  
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| thread count        = 1
 
| thread count        = 1
 
| max cpus            = 1
 
| max cpus            = 1
−
| max memory          = 4 GB
+
| max memory          = 4 GiB
 +
 
  
−
| electrical          = Yes
 
 
| power              =  
 
| power              =  
 
| v core              = 1.40 V
 
| v core              = 1.40 V
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| socket 0 type      = PGA-462
 
| socket 0 type      = PGA-462
 
}}
 
}}
 +
The '''Mobile Duron 850''' based on the {{amd|Morgan|l=core}} (Camaro) core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2001. This model was part of the second generation of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} on a [[180 nm process]], this MPU operated at 850 MHz with a bus capable of 200 MT/s. This particular model (the DHM0850AVS1BM) is sometimes labeled by AMD as {{amd|Athlon}} but is shipped as Duron due to defective or disabled cache. This chip has a core model of "6" instead of "7" unlike the rest of the {{amd|Camaro|l=core}} models.
 +
 +
== Cache ==
 +
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
 +
{{cache info
 +
|l1i cache=64 KiB
 +
|l1i break=1x64 KiB
 +
|l1i desc=2-way set associative
 +
|l1i extra=
 +
|l1d cache=64 KiB
 +
|l1d break=1x64 KiB
 +
|l1d desc=2-way set associative
 +
|l1d extra=
 +
|l2 cache=64 KiB
 +
|l2 break=1x64 KiB
 +
|l2 desc=16-way set associative
 +
|l2 extra=
 +
|l3 cache=
 +
|l3 break=
 +
|l3 desc=
 +
|l3 extra=
 +
}}
 +
 +
== Graphics ==
 +
This SoC has no integrated graphics processing unit.
 +
 +
== Features ==
 +
{{x86 features
 +
| em64t      =
 +
| nx          =
 +
| txt        =
 +
| tsx        =
 +
| vpro        =
 +
| ht          =
 +
| tbt1        =
 +
| tbt2        =
 +
| bpt        =
 +
| vt-x        =
 +
| vt-d        =
 +
| ept        =
 +
| mmx        = Yes
 +
| emmx        = Yes
 +
| 3dnow      = Yes
 +
| e3dnow      = Yes
 +
| sse        = Yes
 +
| sse2        =
 +
| sse3        =
 +
| ssse3      =
 +
| sse4        =
 +
| sse4.1      =
 +
| sse4.2      =
 +
| aes        =
 +
| pclmul      =
 +
| avx        =
 +
| avx2        =
 +
| bmi        =
 +
| bmi1        =
 +
| bmi2        =
 +
| f16c        =
 +
| fma3        =
 +
| mpx        =
 +
| sgx        =
 +
| eist        =
 +
}}
 +
* [[has feature::Halt State]]
 +
* [[has feature::Sleep State]]
 +
 +
== Documents ==
 +
=== DataSheet ===
 +
* [[:File:Mobile AMD Duron Processor Model 7 Data Sheet (December, 2001).pdf|Mobile AMD Duron Processor Model 7 Data Sheet]]; Publication # 24068; Rev: F; Issue Date: December 2001.
 +
 +
== See also ==
 +
* {{amd|Duron}}
 +
* {{intel|Celeron}}

Latest revision as of 16:07, 13 December 2017

Edit Values
Duron 850
General Info
DesignerAMD
ManufacturerAMD
Model NumberDuron 850
Part NumberDHM0850AVS1BM
MarketMobile
Introduction2001 (announced)
2001 (launched)
ShopAmazon
General Specs
FamilyDuron
SeriesDuron Mobile
LockedYes
Frequency850 MHz
Bus typeFSB
Bus speed100 MHz
Bus rate200 MT/s
Clock multiplier8.5
CPUID660
Microarchitecture
MicroarchitectureK7
Core NameMorgan
Core Family6
Core Model6
Core Stepping0, 1
Process180 nm
TechnologyCMOS
Word Size32 bit
Cores1
Threads1
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1.40 V ± 0.1 V
VI/O2.5 V ± 0.25 V
Tcase0 °C – 95 °C
Tstorage-40 °C – 100 °C

The Mobile Duron 850 based on the Morgan (Camaro) core was a 32-bit x86 microprocessor developed by AMD and introduced in 2001. This model was part of the second generation of the Duron family. Designed based on AMD's K7 on a 180 nm process, this MPU operated at 850 MHz with a bus capable of 200 MT/s. This particular model (the DHM0850AVS1BM) is sometimes labeled by AMD as Athlon but is shipped as Duron due to defective or disabled cache. This chip has a core model of "6" instead of "7" unlike the rest of the Camaro models.

Cache[edit]

Main article: K7 § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L1D$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L2$ 64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
1x64 KiB 16-way set associative

Graphics[edit]

This SoC has no integrated graphics processing unit.

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
3DNow!3DNow! Extension
E3DNow!Extended 3DNow! Extension
SSEStreaming SIMD Extensions
  • Halt State
  • Sleep State

Documents[edit]

DataSheet[edit]

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/duron/dhm0850avs1bm&oldid=69970"
Facts about "Duron 850 (Camaro) - AMD"
RDF feed
has featureHalt State + and Sleep State +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +