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Difference between revisions of "exponential technology/x704/466"
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{{expotech title|X704-466}}
 
{{expotech title|X704-466}}
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{{chip
 
| name                = X704-466
 
| name                = X704-466
 
| no image            = Yes
 
| no image            = Yes
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| max memory addr    =  
 
| max memory addr    =  
  
| electrical          = Yes
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| power              = 85 W
 
| power              = 85 W
 
| v core              = 3.6 V
 
| v core              = 3.6 V

Latest revision as of 15:13, 13 December 2017

Edit Values
X704-466
General Info
DesignerExponential Technology
ManufacturerHitachi
Model NumberX704-466
MarketDesktop
IntroductionJanuary 7, 1997 (announced)
General Specs
FamilyX704
Frequency466 MHz
Bus type60x bus
Bus speed100 MHz
Clock multiplier4.6
Microarchitecture
MicroarchitectureX704
PlatformCHRP
Process500 nm
Transistors2,700,000
TechnologyBiCMOS
Die150 mm²
Word Size32 bit
Cores1
Threads1
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation85 W
Vcore3.6 V

X704 466 MHz was a PowerPC-compatible microprocessor operating at 466 MHz announced in January 1997 by Exponential Technology. The company folded before the model ever reaching market (See X704 § History).

Cache[edit]

Main article: X704 § Cache

Level 3 can be provided externally with cache size of 512 KiB to 2 MiB.

Cache Info [Edit Values]
L1I$ 2 KiB
2,048 B
0.00195 MiB
1x2 KiB direct mapped
L1D$ 2 KiB
2,048 B
0.00195 MiB
1x2 KiB direct mapped
L2$ 32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
1x32 KiB 8-way set associative

Graphics[edit]

This SoC has no integrated graphics processing unit.

Features[edit]

  • Fully PowerPC 60x-compatible architecture
  • IEEE 1149.1-compliant JTAG test access port
  • IEEE 754-compliant single-precision and double-precision arithmetic
  • Support for standard PowerPC 60X bus with 64 bits of data and 32 bits of address
  • Support for all PowerPC cache operations
  • Support for PowerEndian and BigEndian modes

Documents[edit]

Manuals[edit]

See also[edit]

l1d$ descriptiondirect mapped +
l1i$ descriptiondirect mapped +
l2$ description8-way set associative +