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Difference between revisions of "intel/celeron/3955u"
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m (Bot: moving all {{mpu}} to {{chip}})
 
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{{intel title|3955U}}
+
{{intel title|Celeron 3955U}}
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{{mpu
+
{{chip
−
| name               = Intel Celeron 3955U
+
|name=Celeron 3955U
−
| no image          = Yes
+
|image=skylake u (front; standard).png
−
| image              =
+
|designer=Intel
−
| image size        =
+
|manufacturer=Intel
−
| caption            =  
+
|model number=3955U
−
| designer           = Intel
+
|part number=FJ8066201931006
−
| manufacturer       = Intel
+
|s-spec=SR2EW
−
| model number       = 3955U
+
|market=Mobile
−
| part number       =  
+
|first announced=August 15, 2015
−
| market             = Mobile
+
|first launched=December 27, 2015
−
| first announced   = August 15, 2015
+
|release price=$107.00
−
| first launched     = December 27, 2015
+
|family=Celeron
−
| last order        =  
+
|series=3000
−
| last shipment      =
+
|locked=Yes
−
 
+
|frequency=2,000 MHz
−
| family             = Celeron
+
|bus type=OPI
−
| series             = 3000
+
|bus rate=4 GT/s
−
| locked             = Yes
+
|clock multiplier=20
−
| frequency         = 2000 MHz
+
|isa=x86-64
−
| turbo frequency    =  
+
|isa family=x86
−
| turbo frequency1  =  
+
|microarch=Skylake
−
| turbo frequency2  =  
+
|core name=Skylake U
−
| turbo frequency3  =  
+
|core family=6
−
| turbo frequency4  =  
+
|core model=78
−
| bus type          =  
+
|core stepping=D1
−
| bus speed          =  
+
|process=14 nm
−
| clock multiplier  = 20
+
|transistors=1,750,000,000
−
| s-spec            =
+
|technology=CMOS
−
 
+
|die area=98.57 mm²
−
| microarch          = Skylake
+
|die length=10.3 mm
−
| platform          =  
+
|die width=9.57 mm
−
| core name          = Skylake U
+
|mcp=Yes
−
| core stepping      =  
+
|die count=2
−
| process            = 14 nm
+
|word size=64 bit
−
| die size          =  
+
|core count=2
−
| word size         = 64 bit
+
|thread count=2
−
| core count         = 2
+
|max cpus=1
−
| thread count       = 2
+
|max memory=32 GiB
−
| max cpus           = 1
+
|v core min=0.55 V
−
| max memory         = 32 GB
+
|v core max=1.52 V
−
 
+
|tdp=15 W
−
| electrical        = Yes
+
|ctdp down=10 W
−
| tdp               = 15 W
+
|tjunc min=0 °C
−
| ctdp down         = 10 W
+
|tjunc max=100 °C
−
| ctdp up            =  
+
|tstorage min=-25 °C
−
| temp max           = 100 °C
+
|tstorage max=125 °C
−
| temp min           =  
+
|package module 1={{packages/intel/fcbga-1356}}
−
 
 
−
| packaging          = Yes
 
−
| package           = FCBGA1356
 
−
| package type      = FCBGA
 
−
| package pitch      =
 
−
| package size      = 42mm X 24mm
 
−
| socket            = BGA1356
 
−
| socket type        = BGA
 
 
}}
 
}}
−
The '''Intel Celeron 3955U''' is a [[dual-core]] [[64-bit architecture|64-bit]] mobile [[microprocessor]] released by [[Intel]] in the third quarter of 2015. The 3955U is designed to replace the {{intel|Broadwell}}-based celeron. Manufactured using 14nm process, the Skylake-based 3955U Celeron processor can be configured to run at down to 10 Watt TDP. This processor, just like its predecessor lack support for any of Intel's advanced technologies such as hyper-threading, trusted execution, transactional synchronization extensions (TSX), and turbo-boost.
+
'''Celeron 3955U''' is a {{arch|64}} [[dual-core]] budget [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 2 GHz. The 3955U has a TDP of 15 W with a configurable TDP-down of 10 W. This chip incorporates the {{intel|HD Graphics 510}} GPU operating at 300 MHz with a burst frequency of 900 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
  
 
== Cache ==
 
== Cache ==
 
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
−
{{cache info
+
{{cache size
 +
|l1 cache=128 KiB
 
|l1i cache=64 KiB
 
|l1i cache=64 KiB
 
|l1i break=2x32 KiB
 
|l1i break=2x32 KiB
 +
|l1i desc=8-way set associative
 
|l1d cache=64 KiB
 
|l1d cache=64 KiB
 
|l1d break=2x32 KiB
 
|l1d break=2x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 
|l2 cache=512 KiB
 
|l2 cache=512 KiB
 
|l2 break=2x256 KiB
 
|l2 break=2x256 KiB
 
|l2 desc=4-way set associative
 
|l2 desc=4-way set associative
 +
|l2 policy=write-back
 
|l3 cache=2 MiB
 
|l3 cache=2 MiB
 +
|l3 break=2x1 MiB
 +
|l3 policy=write-back
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2133
 +
|type 2=LPDDR3-1866
 +
|type 3=DDR3L-1600
 +
|ecc=No
 +
|max mem=32 GiB
 +
|controllers=1
 +
|channels=2
 +
|max bandwidth=31.79 GiB/s
 +
|bandwidth schan=15.89 GiB/s
 +
|bandwidth dchan=31.79 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 12
 +
| pcie config        = 1x4
 +
| pcie config 2      = 2x2
 +
| pcie config 3      = 1x2+2x1
 +
| pcie config 4      = 4x1
 
}}
 
}}
  
 
== Graphics ==
 
== Graphics ==
−
{{integrated graphic
+
{{integrated graphics
−
| gpu               = Intel HD Graphics 510
+
| gpu                 = HD Graphics 510
−
| displays           = 3
+
| device id          = 0x1906
−
| frequency         = 300 MHz
+
| designer            = Intel
−
| max frequency     = 900 MHz
+
| execution units    = 12
−
| max memory         = 1700 MB
+
| max displays       = 3
−
| output edp         = Yes
+
| max memory          = 32 GiB
−
| output dp         = Yes
+
| frequency           = 300 MHz
−
| output hdmi       = Yes
+
| max frequency       = 900 MHz
−
| output vga         =  
+
 
−
| output dvi         = Yes
+
| output crt          =
 +
| output sdvo         =  
 +
| output dsi          =
 +
| output edp         = Yes
 +
| output dp           = Yes
 +
| output hdmi         = Yes
 +
| output vga         =  
 +
| output dvi         = Yes
 +
 
 
| directx ver        = 12
 
| directx ver        = 12
 
| opengl ver        = 4.4
 
| opengl ver        = 4.4
 +
| opencl ver        = 2.0
 +
| hdmi ver          = 1.4a
 +
| dp ver            = 1.2
 +
| edp ver            = 1.3
 
| max res hdmi      = 4096x2304
 
| max res hdmi      = 4096x2304
 
| max res hdmi freq  = 24 Hz
 
| max res hdmi freq  = 24 Hz
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| max res vga        =  
 
| max res vga        =  
 
| max res vga freq  =  
 
| max res vga freq  =  
−
}}
 
  
−
== Memory controller ==
+
| features             = Yes
−
{{integrated memory controller
+
| intel quick sync    = Yes
−
| type              = DDR4-1866
+
| intel intru 3d      =  
−
| type 1             = DDR4-2133
+
| intel insider       =  
−
| type 2            = LPDDR3-1600
+
| intel widi           =  
−
| type 3            = LPDDR3-1866
+
| intel fdi            =  
−
| controllers       = 1
+
| intel clear video    =  
−
| channels           = 2
+
| intel clear video hd = Yes
−
| ecc support        =  
 
−
| max bandwidth      = 34,100 MB/s
 
−
| max memory        = 32,768 MB
 
 
}}
 
}}
 +
{{skylake hardware accelerated video table|col=1}}
  
−
== Expansions ==
+
== Features ==  
−
{{mpu expansions
+
{{x86 features
−
| pcie revision      = 2.0
+
|real=Yes
−
| pcie lanes        = 10
+
|protected=Yes
−
| pcie config        = 1x4
+
|smm=Yes
−
| pcie config 1      = 2x2
+
|fpu=Yes
−
| pcie config 2      = 1x2+2x1
+
|x8616=Yes
−
| pcie config 3      = 4x1
+
|x8632=Yes
−
}}
+
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=No
 +
|avx2=No
  
−
== Features ==
+
|abm=Yes
−
{{mpu features
+
|tbm=No
−
| em64t    = Yes
+
|bmi1=Yes
−
| nx        = Yes
+
|bmi2=Yes
−
| txt      =  
+
|fma3=No
−
| tsx      =  
+
|fma4=No
−
| ht        =  
+
|aes=Yes
−
| tbt2     =  
+
|rdrand=Yes
−
| vt-x      = Yes
+
|sha=No
−
| vt-d      = Yes
+
|xop=No
−
| mmx      = Yes
+
|adx=Yes
−
| sse      = Yes
+
|clmul=Yes
−
| sse2      = Yes
+
|f16c=Yes
−
| sse3      = Yes
+
|tbt1=No
−
| ssse3    = Yes
+
|tbt2=No
−
| sse4      = Yes
+
|tbmt3=No
−
| sse4.1    = Yes
+
|bpt=No
−
| sse4.2    = Yes
+
|eist=Yes
−
| aes      = Yes
+
|sst=No
−
| avx      =  
+
|flex=Yes
−
| avx2      =  
+
|fastmem=No
−
| bmi      =  
+
|isrt=Yes
−
| bmi1      =  
+
|sba=No
−
| bmi2      =  
+
|mwt=Yes
−
| f16c      =  
+
|sipp=No
−
| fma3      =  
+
|att=No
−
| sgx      = Yes
+
|ipt=Yes
−
| eist      = Yes
+
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=Yes
 +
|securekey=Yes
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 
}}
 
}}

Latest revision as of 15:15, 13 December 2017

Edit Values
Celeron 3955U
skylake u (front; standard).png
General Info
DesignerIntel
ManufacturerIntel
Model Number3955U
Part NumberFJ8066201931006
S-SpecSR2EW
MarketMobile
IntroductionAugust 15, 2015 (announced)
December 27, 2015 (launched)
Release Price$107.00
ShopAmazon
General Specs
FamilyCeleron
Series3000
LockedYes
Frequency2,000 MHz
Bus typeOPI
Bus rate4 GT/s
Clock multiplier20
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake
Core NameSkylake U
Core Family6
Core Model78
Core SteppingD1
Process14 nm
Transistors1,750,000,000
TechnologyCMOS
Die98.57 mm²
10.3 mm × 9.57 mm
MCPYes (2 dies)
Word Size64 bit
Cores2
Threads2
Max Memory32 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore0.55 V-1.52 V
TDP15 W
cTDP down10 W
Tjunction0 °C – 100 °C
Tstorage-25 °C – 125 °C
Packaging
PackageFCBGA-1356 (BGA)
Dimension42 mm x 24 mm x 1.3 mm
Pitch0.65 mm
Ball Count1356
Ball CompSAC405
InterconnectBGA-1356

Celeron 3955U is a 64-bit dual-core budget x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2 GHz. The 3955U has a TDP of 15 W with a configurable TDP-down of 10 W. This chip incorporates the HD Graphics 510 GPU operating at 300 MHz with a burst frequency of 900 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB write-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133, LPDDR3-1866, DDR3L-1600
Supports ECCNo
Max Mem32 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes12
Configs1x4, 2x2, 1x2+2x1, 4x1


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics 510
DesignerIntelDevice ID0x1906
Execution Units12Max Displays3
Max Memory32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
Frequency300 MHz
0.3 GHz
300,000 KHz
Burst Frequency900 MHz
0.9 GHz
900,000 KHz
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4096x2304 @24 Hz
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.3
HDMI1.4a
Additional Features
Intel Quick Sync Video
Intel Clear Video HD

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
EISTEnhanced SpeedStep Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
Flex MemoryFlex Memory Access
ISRTSmart Response Technology
MWTMy WiFi Technology
IPTIdentity Protection Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/3955u&oldid=70436"
Facts about "Celeron 3955U - Intel"
RDF feed
has featureintegrated gpu +
integrated gpuIntel HD Graphics 510 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu max frequency900 MHz (0.9 GHz, 900,000 KHz) +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +