From WikiChip
Difference between revisions of "intel/atom x5/x5-e8000"
< intel‎ | atom x5

 
(8 intermediate revisions by 3 users not shown)
Line 1: Line 1:
 
{{intel title|Atom x5-E8000}}
 
{{intel title|Atom x5-E8000}}
−
{{mpu
+
{{chip
−
| name               = Intel Atom x5-E8000
+
|name=Intel Atom x5-E8000
−
| no image           = Yes
+
|no image=Yes
−
| image              =
+
|designer=Intel
−
| image size          =
+
|manufacturer=Intel
−
| caption            =  
+
|model number=x5-E8000
−
| manufacturer       = Intel
+
|part number=FH8066501715946
−
| model number       = x5-E8000
+
|s-spec=SR2LV
−
| part number         = FH8066501715946
+
|market=Embedded
−
| market             = Embedded
+
|first announced=February 8, 2016
−
| first announced     = February 8, 2016  
+
|first launched=February 8, 2016
−
| first launched     = February 8, 2016  
+
|release price=$39.00
−
| last order          =
+
|family=Atom x5
−
| last shipment      =  
+
|series=E8000
−
 
+
|locked=Yes
−
| family             = Atom x5
+
|frequency=1040 MHz
−
| series             = E8000
+
|turbo frequency1=2000 MHz
−
| locked             = Yes
+
|turbo frequency=Yes
−
| frequency           = 1040 MHz
+
|clock multiplier=10
−
| turbo frequency    = Yes
+
|microarch=Airmont
−
| turbo frequency1   = 2000 MHz
+
|platform=Braswell
−
| bus type            =
+
|core name=Braswell
−
| bus speed          =  
+
|core stepping=D1
−
| clock multiplier   = 10
+
|process=14 nm
−
| s-spec              = SR2LV
+
|technology=CMOS
−
| s-spec es          =
+
|word size=64 bit
−
| s-spec qs          =
+
|core count=4
−
 
+
|thread count=4
−
| microarch           = Airmont
+
|max cpus=1
−
| platform           = Braswell
+
|max memory=8 GiB
−
| core name           = Braswell
+
|tdp=5 W
−
| core stepping       = D1
+
|temp min=0 °C
−
| process             = 14 nm
+
|temp max=90 °C
−
| transistors        =
+
|packaging=Yes
−
| technology         = CMOS
+
|package=FCBGA-1170
−
| die size            =
+
|package size=25mm x 27mm
−
| word size           = 64 bit
+
|socket=BGA-1170
−
| core count         = 4
+
|socket type=BGA
−
| thread count       = 4
 
−
| max cpus           = 1
 
−
| max memory         = 8 GB
 
−
| max memory addr    =
 
−
 
 
−
| electrical          = Yes
 
−
| power              =
 
−
| sdp                =
 
−
| tdp                 = 5 W
 
−
| ctdp down          =
 
−
| ctdp down frequency =
 
−
| ctdp up            =
 
−
| temp max           = 90 °C
 
−
| temp min            = 0 °C
 
−
 
 
−
| packaging           = Yes
 
−
| package             = FCBGA-1170
 
−
| package pitch      =
 
−
| package size       = 25mm x 27mm
 
−
| socket             = BGA-1170
 
−
| socket type         = BGA
 
 
}}
 
}}
−
The '''Atom x5-E8000''' is a {{arch|64}} quad-core [[system on a chip]] introduce by [[Intel]] in early 2016. This ultra-low power SoC has a thermal design power of just 5 W and operates at a base frequency of 1.04 GHz with a burst up to 2.0 GHz and supports up to 8 GB of memory. This chip incorporates the {{intel|HD Graphics (Braswell)}} GPU.
+
The '''Atom x5-E8000''' is a {{arch|64}} quad-core [[system on a chip]] introduce by [[Intel]] in early 2016. This ultra-low power SoC has a thermal design power of just 5 W and operates at a base frequency of 1.04 GHz with a burst up to 2.0 GHz and supports up to 8 GiB of memory. This chip incorporates the {{intel|HD Graphics (Braswell)}} GPU.
  
 
== Cache ==
 
== Cache ==
−
{{main|intel/microarchitectures/airmont#Memory_Hierarchy|l1=Airmont's Cache}}
+
{{main|intel/microarchitectures/airmont#Memory_Hierarchy|l1=Airmont § Cache}}
 
{{cache info
 
{{cache info
−
|l1i cache=128 KB
+
|l1i cache=128 KiB
−
|l1i break=4x32 KB
+
|l1i break=4x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
 
|l1i extra=(per core)
 
|l1i extra=(per core)
−
|l1d cache=96 KB
+
|l1d cache=96 KiB
−
|l1d break=4x24 KB
+
|l1d break=4x24 KiB
 
|l1d desc=6-way set associative
 
|l1d desc=6-way set associative
 
|l1d extra=(per core)
 
|l1d extra=(per core)
−
|l2 cache=2 MB
+
|l2 cache=2 MiB
−
|l2 break=2x1 MB
+
|l2 break=2x1 MiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 extra=(per 2 cores)
 
|l2 extra=(per 2 cores)
Line 99: Line 78:
 
| frequency          = 320 MHz
 
| frequency          = 320 MHz
 
| max frequency      =  
 
| max frequency      =  
−
| max memory          = 8 GB
+
| max memory          = 8 GiB
 
| output edp          = Yes
 
| output edp          = Yes
 
| output dp          =  
 
| output dp          =  
Line 136: Line 115:
  
 
== Expansions ==
 
== Expansions ==
−
{{mpu expansions
+
{{expansions
 
| pcie revision      = 2.0
 
| pcie revision      = 2.0
 
| pcie lanes        = 4
 
| pcie lanes        = 4
Line 146: Line 125:
  
 
== Features ==
 
== Features ==
−
{{mpu features
+
{{x86 features
 
| em64t    = Yes
 
| em64t    = Yes
 
| nx        = Yes
 
| nx        = Yes

Latest revision as of 16:42, 27 March 2018

Edit Values
Intel Atom x5-E8000
General Info
DesignerIntel
ManufacturerIntel
Model Numberx5-E8000
Part NumberFH8066501715946
S-SpecSR2LV
MarketEmbedded
IntroductionFebruary 8, 2016 (announced)
February 8, 2016 (launched)
Release Price$39.00
ShopAmazon
General Specs
FamilyAtom x5
SeriesE8000
LockedYes
Frequency1040 MHz
Turbo FrequencyYes
Turbo Frequency2000 MHz (1 core)
Clock multiplier10
Microarchitecture
MicroarchitectureAirmont
PlatformBraswell
Core NameBraswell
Core SteppingD1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads4
Max Memory8 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP5 W
OP Temperature0 °C – 90 °C

The Atom x5-E8000 is a 64-bit quad-core system on a chip introduce by Intel in early 2016. This ultra-low power SoC has a thermal design power of just 5 W and operates at a base frequency of 1.04 GHz with a burst up to 2.0 GHz and supports up to 8 GiB of memory. This chip incorporates the HD Graphics (Braswell) GPU.

Cache[edit]

Main article: Airmont § Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core)
L1D$ 96 KiB
98,304 B
0.0938 MiB
4x24 KiB 6-way set associative (per core)
L2$ 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
2x1 MiB 16-way set associative (per 2 cores)
L3$ 0 KiB
0 MiB
0 B
0 GiB
No L3$

Memory controller[edit]

Integrated Memory Controller
Type DDR3L-1600
Controllers 1
Channels 2
ECC Support No
Bandwidth (single) 12,800 MB/s
Bandwidth (dual) 25,600 MB/s
Max memory 8,192 MB

Graphics[edit]

Integrated Graphic Information
GPU HD Graphics (Braswell)
Execution Units 12
Displays 3
Frequency 320 MHz
0.32 GHz
320,000 KHz
Max memory 8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
Output Embedded DisplayPort, HDMI
DirectX 11.2
OpenGL 4.4
OpenCL 2.0
DVI 1.4b
HDMI 1.4b
DVI 1.4b
Vulkan 1.0
DP 1.1a
eDP 1.3
Max HDMI Res 1920x1080 @120 Hz, 3840x2160 @60 Hz
Max DVI Res 1920x1080 @120 Hz, 3840x2160 @60 Hz
Max DSI Res 2560x1600 @60 Hz
Max eDP Res 2560x1600 @60 Hz
  • Video decode hardware acceleration including support for H.263, MPEG4, H.264, H.265 (HEVC), VP8, VP9, MVC, MPEG2, VC1, JPEG.
  • Video encode hardware acceleration including support for H.264, H.263, VP8, MVC, JPEG.

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes4
Configs1x4, 1x2 + 2x1, 4x1


Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/atom_x5/x5-e8000&oldid=75564"
Facts about "Atom x5-E8000 - Intel"
RDF feed
has featureintegrated gpu +
integrated gpuHD Graphics (Braswell) +
integrated gpu base frequency320 MHz (0.32 GHz, 320,000 KHz) +
l1d$ description6-way set associative +
l1i$ description8-way set associative +
l2$ description16-way set associative +
l3$ descriptionNo L3$ +
l3$ size0 MiB (0 KiB, 0 B, 0 GiB) +