From WikiChip
Difference between revisions of "amd/k6-iii+/amd-k6-iiie+-400icr"
< amd‎ | k6-iii+

(Replaced package module by package name.)
 
(8 intermediate revisions by 4 users not shown)
Line 1: Line 1:
 
{{amd title|AMD-K6-IIIE+/400ICR}}
 
{{amd title|AMD-K6-IIIE+/400ICR}}
−
{{mpu
+
{{chip
 
| name                = AMD-K6-IIIE+/400ICR
 
| name                = AMD-K6-IIIE+/400ICR
 
| no image            = Yes
 
| no image            = Yes
Line 10: Line 10:
 
| model number        = AMD-K6-IIIE+/400ICR
 
| model number        = AMD-K6-IIIE+/400ICR
 
| part number        = AMD-K6-IIIE+/400ICR
 
| part number        = AMD-K6-IIIE+/400ICR
−
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Embedded
 
| market              = Embedded
 
| first announced    = September 25, 2000
 
| first announced    = September 25, 2000
Line 49: Line 49:
 
| thread count        = 1
 
| thread count        = 1
 
| max cpus            = 1
 
| max cpus            = 1
−
| max memory          = 4 GB
+
| max memory          = 4 GiB
 +
 
  
−
| electrical          = Yes
 
 
| power              =  
 
| power              =  
 
| v core              = 2.0 V
 
| v core              = 2.0 V
Line 68: Line 68:
 
| tstorage max        = 150 °C
 
| tstorage max        = 150 °C
  
−
| packaging          = Yes
+
| package name 1     = amd,obga-349
−
| package 0          = OBGA-349
 
−
| package 0 type     = OBGA
 
−
| package 0 pins      = 349
 
−
| package 0 pitch    = 1.27 mm
 
−
| package 0 width    = 25 mm
 
−
| package 0 length    = 25 mm
 
−
| package 0 height    = 1.41 mm
 
−
| socket 0            = BGA-349
 
−
| socket 0 type      = BGA
 
 
}}
 
}}
 
'''AMD-K6-IIIE+/400ICR''' is a {{arch|32}} [[x86]] embedded microprocessor designed by [[AMD]] and introduced in late [[2000]]. This MPU which was manufactured on a [[0.18 µm process]], based on {{amd|microarchitectures/k6-iii|K6-III microarchitecture}}, operated at 400 MHz with a bus of 100 MHz and a multiplier of 4. This chip had a TDP of 9.5 W.
 
'''AMD-K6-IIIE+/400ICR''' is a {{arch|32}} [[x86]] embedded microprocessor designed by [[AMD]] and introduced in late [[2000]]. This MPU which was manufactured on a [[0.18 µm process]], based on {{amd|microarchitectures/k6-iii|K6-III microarchitecture}}, operated at 400 MHz with a bus of 100 MHz and a multiplier of 4. This chip had a TDP of 9.5 W.
Line 83: Line 74:
 
== Cache ==
 
== Cache ==
 
{{main|amd/microarchitectures/k6-iii#Memory_Hierarchy|l1=K6-III § Cache}}
 
{{main|amd/microarchitectures/k6-iii#Memory_Hierarchy|l1=K6-III § Cache}}
−
[[L3$]] can be 512 KB to 2 MB, depending on manufacturer and [[motherboard]] model. L3$ is off-chip.
+
[[L3$]] can be 512 KiB to 2 MiB, depending on manufacturer and [[motherboard]] model. L3$ is off-chip.
 
{{cache info
 
{{cache info
−
|l1i cache=32 KB
+
|l1i cache=32 KiB
−
|l1i break=1x32 KB
+
|l1i break=1x32 KiB
 
|l1i desc=2-way set associative
 
|l1i desc=2-way set associative
 
|l1i extra=
 
|l1i extra=
−
|l1d cache=32 KB
+
|l1d cache=32 KiB
−
|l1d break=1x32 KB
+
|l1d break=1x32 KiB
 
|l1d desc=2-way set associative
 
|l1d desc=2-way set associative
 
|l1d extra=
 
|l1d extra=
−
|l2 cache=256 KB
+
|l2 cache=256 KiB
−
|l2 break=1x256
+
|l2 break=1x256 KiB
 
|l2 desc=4-way set associative
 
|l2 desc=4-way set associative
 
|l2 extra=(shared)
 
|l2 extra=(shared)
Line 104: Line 95:
  
 
== Graphics ==
 
== Graphics ==
−
This SoC has no integrated graphics processing unit.
+
This processors has no integrated graphics processing unit.
  
 
== Features ==
 
== Features ==
−
{{mpu features
+
{{x86 features
 
| mmx        = Yes
 
| mmx        = Yes
 
| emmx        = Yes
 
| emmx        = Yes

Latest revision as of 12:42, 18 March 2023

Edit Values
AMD-K6-IIIE+/400ICR
General Info
DesignerAMD
ManufacturerAMD
Model NumberAMD-K6-IIIE+/400ICR
Part NumberAMD-K6-IIIE+/400ICR
MarketEmbedded
IntroductionSeptember 25, 2000 (announced)
September 25, 2000 (launched)
ShopAmazon
General Specs
FamilyK6-III+
SeriesK6-III+ Embedded
Frequency399.99 MHz
Bus typeFSB
Bus speed99.99 MHz
Bus rate99.99 MT/s
Clock multiplier4
CPUID5D0
Microarchitecture
MicroarchitectureK6-III
PlatformSuper 7
Core Family5
Core Model13
Core Stepping0, 1, 2, 3
Process0.18 µm
Transistors21,400,000
TechnologyCMOS
Word Size32 bit
Cores1
Threads1
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore2.0 V ± 0.1 V
VI/O3.3675 V ± 7%
TDP9.5 W
Tcase0 °C – 70 °C
Tstorage-65 °C – 150 °C
Packaging
PackageOBGA-349
Package TypeOrganic Ball Grid Array
Dimension25 mm × 25 mm
Pitch1.27 mm
Contacts349

AMD-K6-IIIE+/400ICR is a 32-bit x86 embedded microprocessor designed by AMD and introduced in late 2000. This MPU which was manufactured on a 0.18 µm process, based on K6-III microarchitecture, operated at 400 MHz with a bus of 100 MHz and a multiplier of 4. This chip had a TDP of 9.5 W.

Cache[edit]

Main article: K6-III § Cache

L3$ can be 512 KiB to 2 MiB, depending on manufacturer and motherboard model. L3$ is off-chip.

Cache Info [Edit Values]
L1I$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative
L1D$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative
L2$ 256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
1x256 KiB 4-way set associative (shared)

Graphics[edit]

This processors has no integrated graphics processing unit.

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
3DNow!3DNow! Extension
E3DNow!Extended 3DNow! Extension
  • Auto-power down state
  • Stop clock state
  • Halt state
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/k6-iii%2B/amd-k6-iiie%2B-400icr&oldid=101344"
Facts about "AMD-K6-IIIE+/400ICR - AMD"
RDF feed
l1d$ description2-way set associative +
l1i$ description2-way set associative +
l2$ description4-way set associative +