Semiconductor & Computer Engineering
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Difference between revisions of "amd/k6/amd-k6-233anr"
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{{amd title|AMD-K6-233ANR}} | {{amd title|AMD-K6-233ANR}} | ||
| − | {{ | + | {{chip |
| name = AMD-K6-233ANR | | name = AMD-K6-233ANR | ||
| − | | no image = | + | | no image = |
| − | | image = | + | | image = KL AMD LogoK6 K6.jpg |
| image size = | | image size = | ||
| − | | caption = | + | | caption = 233ANR, Week 46, 1997 |
| designer = AMD | | designer = AMD | ||
| manufacturer = AMD | | manufacturer = AMD | ||
| Line 43: | Line 43: | ||
| thread count = 1 | | thread count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| max memory addr = | | max memory addr = | ||
| − | + | ||
| power = 28.3 W | | power = 28.3 W | ||
| v core = 2.9 V | | v core = 2.9 V | ||
| Line 76: | Line 76: | ||
== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k6#Memory_Hierarchy|l1=K6 § Cache}} | {{main|amd/microarchitectures/k6#Memory_Hierarchy|l1=K6 § Cache}} | ||
| − | [[L2$]] can be 256 | + | [[L2$]] can be 256 KiB to 1 MiB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip. |
{{cache info | {{cache info | ||
| − | |l1i cache=32 | + | |l1i cache=32 KiB |
| − | |l1i break=1x32 | + | |l1i break=1x32 KiB |
|l1i desc=2-way set associative | |l1i desc=2-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=32 | + | |l1d cache=32 KiB |
| − | |l1d break=1x32 | + | |l1d break=1x32 KiB |
|l1d desc=2-way set associative | |l1d desc=2-way set associative | ||
|l1d extra= | |l1d extra= | ||
| Line 100: | Line 100: | ||
== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| mmx = true | | mmx = true | ||
}} | }} | ||
* Auto-power down state | * Auto-power down state | ||
* Stop clock state | * Stop clock state | ||
| + | |||
| + | == Documents == | ||
| + | === DataSheet === | ||
| + | * [[:File:AMD-K6 Processor DataSheet (June, 1997).pdf|AMD-K6 MMX Enhanced Processor Multimedia Technology]]; Publication #20695 Revision E/0; June 1997 | ||
Latest revision as of 15:09, 13 December 2017
| Edit Values | |
| AMD-K6-233ANR | |
 | |
| 233ANR, Week 46, 1997 | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | AMD-K6-233ANR |
| Part Number | AMD-K6-233ANR |
| Market | Desktop |
| Introduction | May, 1997 (announced) May, 1997 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | K6 |
| Series | Desktop K6 |
| Locked | No |
| Frequency | 233.33 MHz |
| Bus type | FSB |
| Bus speed | 66.66 MHz |
| Bus rate | 66.66 MT/s |
| Clock multiplier | 3.5 |
| CPUID | 560 |
| Microarchitecture | |
| Microarchitecture | K6 |
| Core Name | 6k86 |
| Core Family | 5 |
| Core Model | 6 |
| Process | 350 nm |
| Transistors | 8,800,000 |
| Technology | CMOS |
| Die | 162 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 28.3 W |
| Vcore | 2.9 V ± 5% |
| VI/O | 3.3 V ± 5% |
| Tcase | 0 °C – 70 °C |
| Tstorage | -65 °C – 150 °C |
AMD-K6-233ANR was a 32-bit x86 microprocessor designed by AMD and introduced in early 1997. This chip, which was based on AMD's new K6 microarchitecture, operated at 233 MHz and dissipated a maximum of 28.3 W.
Contents
Cache[edit]
- Main article: K6 § Cache
L2$ can be 256 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
| L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
|
|
|
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- Auto-power down state
- Stop clock state
Documents[edit]
DataSheet[edit]
- AMD-K6 MMX Enhanced Processor Multimedia Technology; Publication #20695 Revision E/0; June 1997
Facts about "AMD-K6-233ANR - AMD"
| l1d$ description | 2-way set associative + |
| l1i$ description | 2-way set associative + |