Semiconductor & Computer Engineering
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Difference between revisions of "intrinsity/fastmath/fastmath-lp"
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{{intrinsity title|FastMATH-LP}} | {{intrinsity title|FastMATH-LP}} | ||
| − | {{ | + | {{chip |
| name = FastMATH-LP | | name = FastMATH-LP | ||
| − | | no image = | + | | no image = |
| − | | image = | + | | image = fastmath-lp chip.gif |
| image size = | | image size = | ||
| caption = | | caption = | ||
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| model number = FastMATH-LP | | model number = FastMATH-LP | ||
| part number = | | part number = | ||
| − | | part number | + | | part number 2 = |
| market = Embedded | | market = Embedded | ||
| first announced = 2002 | | first announced = 2002 | ||
| Line 41: | Line 41: | ||
| thread count = 1 | | thread count = 1 | ||
| max cpus = | | max cpus = | ||
| − | | max memory = 1 | + | | max memory = 1 GiB |
| max memory addr = | | max memory addr = | ||
| − | + | ||
| power = 6 W | | power = 6 W | ||
| v core = 0.85 V | | v core = 0.85 V | ||
| Line 79: | Line 79: | ||
{{main|intrinsity/microarchitectures/fastmath#Memory_Hierarchy|l1=FastMATH § Cache}} | {{main|intrinsity/microarchitectures/fastmath#Memory_Hierarchy|l1=FastMATH § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1i cache=16 | + | |l1i cache=16 KiB |
| − | |l1i break=1x16 | + | |l1i break=1x16 KiB |
|l1i desc=256 blocks × 16 words/block | |l1i desc=256 blocks × 16 words/block | ||
| − | + | |l1d cache=16 KiB | |
| − | |l1d cache=16 | + | |l1d break=1x16 KiB |
| − | |l1d break=1x16 | ||
|l1d desc=256 blocks × 16 words/block | |l1d desc=256 blocks × 16 words/block | ||
|l1d extra=write-through or write-back mode | |l1d extra=write-through or write-back mode | ||
| − | |l2 cache=1 | + | |l2 cache=1 MiB |
| − | |l2 break=1x1 | + | |l2 break=1x1 MiB |
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
| − | |l2 extra=(configurable as SRAM in 256 | + | |l2 extra=(configurable as SRAM in 256 KiB increments) |
| − | |||
| − | |||
| − | |||
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}} | }} | ||
Latest revision as of 15:31, 13 December 2017
| Edit Values | |
| FastMATH-LP | |
 | |
| General Info | |
| Designer | Intrinsity |
| Manufacturer | TSMC |
| Model Number | FastMATH-LP |
| Market | Embedded |
| Introduction | 2002 (announced) 2003 (launched) |
| General Specs | |
| Family | FastMATH |
| Frequency | 1,000 MHz |
| Bus type | RapidIO |
| Bus speed | 500 MHz |
| Bus rate | 4 GT/s |
| Microarchitecture | |
| Microarchitecture | FashMATH |
| Process | 130 nm |
| Technology | Dynamic CMOS |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 1 GiB |
| Electrical | |
| Power dissipation | 6 W |
| Vcore | 0.85 V |
The FastMATH-LP was a microprocessor developed by Intrinsity operating at 1 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.
Contents
Cache[edit]
- Main article: FastMATH § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 256 blocks × 16 words/block |
| L1D$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 256 blocks × 16 words/block write-through or write-back mode |
| L2$ | 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB |
1x1 MiB 4-way set associative (configurable as SRAM in 256 KiB increments) |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Memory controller[edit]
| Integrated Memory Controller | |
| Type | DDR-400 |
| Controllers | 1 |
| Channels | 2 |
| Max memory | 1 GB |
Matrix and Vector Unit[edit]
- SIMD architecture
- Operates on 4x4 array of 32-bit elements
- Fixed-point matrix, vector, and scalar data types
Features[edit]
- JTAG interface
- 8-bit or 32-bit wide bus operates up to 66 MHz
Documents[edit]
Manuals[edit]
Facts about "FastMATH-LP - Intrinsity"
| has feature | JTAG + |
| l1d$ description | 256 blocks × 16 words/block + |
| l1i$ description | 256 blocks × 16 words/block + |
| l2$ description | 4-way set associative + |