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Difference between revisions of "ambric/am2000/am2045b"
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{{ambric title|Am2045B}} | {{ambric title|Am2045B}} | ||
− | {{ | + | {{chip |
| name = Am2045B | | name = Am2045B | ||
| no image = Yes | | no image = Yes | ||
Line 37: | Line 37: | ||
| die size = | | die size = | ||
| word size = 32 bit | | word size = 32 bit | ||
− | | core count = | + | | core count = 344 |
| thread count = | | thread count = | ||
| max cpus = | | max cpus = | ||
− | | max memory = 4 | + | | max memory = 4 GiB |
| electrical = | | electrical = | ||
Line 72: | Line 72: | ||
| socket 0 type = BGA | | socket 0 type = BGA | ||
}} | }} | ||
− | '''Am2045B''' was [[Ambric]]'s flagship [[MPPA]] introduced in late 2007. This model was made of | + | '''Am2045B''' was [[Ambric]]'s flagship [[MPPA]] introduced in late 2007. This model was made of {{ambric|am2000#Architecture|43 Brics}} arranged as a grid, making up a total of 344 {{arch|32}} [[RICS]]-like cores operating asynchronously at 1-350 MHz. This was an enhanced version of the {{\\|Am2045|original}} which featured a higher bandwidth [[network on a chip]] (Ambric claimed up to 40 percent improvement), operated at higher frequency, and provided up to 1.2 trillion operations per seconds theoretical peak computation. This model also had lower power consumption over the original. |
+ | Note that some early models might have had only 42 brics at one point for 336 cores. | ||
== Architecture == | == Architecture == | ||
{{main|ambric/am2000#Architecture|l1=Am2000 § Architecture}} | {{main|ambric/am2000#Architecture|l1=Am2000 § Architecture}} | ||
− | The Am2045B is made of | + | The Am2045B is made of 43 homogeneous 'Brics' laid out in a grid to form 344 cores. |
General layout: | General layout: | ||
− | * | + | * 43x Brics |
** 2x Computer Unit (CU) | ** 2x Computer Unit (CU) | ||
*** 2x SRD {{arch|32}} CPU | *** 2x SRD {{arch|32}} CPU | ||
Line 95: | Line 96: | ||
| bandwidth schan = | | bandwidth schan = | ||
| bandwidth dchan = | | bandwidth dchan = | ||
− | | max memory = 4 | + | | max memory = 4 GiB |
}} | }} | ||
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* 128x [[has feature::GPIO]] @ 100 MHz | * 128x [[has feature::GPIO]] @ 100 MHz | ||
* [[has feature::serial flash]] | * [[has feature::serial flash]] | ||
+ | |||
+ | == Die Shot == | ||
+ | {| | ||
+ | | [[File:Am2045 die shot.png]] || [[File:Am2045 die shot (annotated).png]] | ||
+ | |} |
Latest revision as of 15:16, 13 December 2017
Edit Values | |
Am2045B | |
General Info | |
Designer | Ambric |
Model Number | Am2045B |
Part Number | Am2045B |
Market | Embedded |
Introduction | November 15, 2007 (announced) November 15, 2007 (launched) |
End-of-life | 2012 (last order) 2012 (last shipment) |
General Specs | |
Family | Am2000 |
Series | Gen 2 |
Locked | No |
Frequency | 350 MHz |
Bus speed | 100 MHz |
Clock multiplier | 3.5 |
Microarchitecture | |
Microarchitecture | Ambric |
Process | 130 nm |
Transistors | 180,000,000 |
Technology | CMOS |
Word Size | 32 bit |
Cores | 344 |
Max Memory | 4 GiB |
Am2045B was Ambric's flagship MPPA introduced in late 2007. This model was made of 43 Brics arranged as a grid, making up a total of 344 32-bit RICS-like cores operating asynchronously at 1-350 MHz. This was an enhanced version of the original which featured a higher bandwidth network on a chip (Ambric claimed up to 40 percent improvement), operated at higher frequency, and provided up to 1.2 trillion operations per seconds theoretical peak computation. This model also had lower power consumption over the original.
Note that some early models might have had only 42 brics at one point for 336 cores.
Architecture[edit]
- Main article: Am2000 § Architecture
The Am2045B is made of 43 homogeneous 'Brics' laid out in a grid to form 344 cores.
General layout:
- 43x Brics
Memory controller[edit]
Integrated Memory Controller | |
Type | DDR2-400 |
Controllers | 2 |
Channels | 1 |
Max memory | 4 GiB |
Expansions[edit]
- PCIe
- JTAG
- 128x GPIO @ 100 MHz
- serial flash
Die Shot[edit]
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