Semiconductor & Computer Engineering
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Difference between revisions of "ambric/am2000/am2016"
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{{ambric title|Am2016}} | {{ambric title|Am2016}} | ||
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| name = Am2016 | | name = Am2016 | ||
| no image = Yes | | no image = Yes | ||
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| thread count = | | thread count = | ||
| max cpus = | | max cpus = | ||
| − | | max memory = | + | | max memory = 4 GiB |
| electrical = | | electrical = | ||
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| socket 0 type = | | socket 0 type = | ||
}} | }} | ||
| + | '''Am2016''' was an [[MPPA]] introduced in late 2007 by [[Ambric]]. This model was made of roughly {{ambric|am2000#Architecture|16 Brics}} arranged as a grid, making up a total of 120 {{arch|32}} [[RICS]]-like cores operating asynchronously at 1-350 MHz. | ||
| + | |||
| + | == Architecture == | ||
| + | {{main|ambric/am2000#Architecture|l1=Am2000 § Architecture}} | ||
| + | The Am2016 is made of 16 homogeneous 'Brics' laid out in a grid to form 120 cores. | ||
| + | |||
| + | General layout: | ||
| + | * 16x Brics | ||
| + | ** 2x Computer Unit (CU) | ||
| + | *** 2x SRD {{arch|32}} CPU | ||
| + | *** 2x RD {{arch|32}} CPU | ||
| + | ** 2x [[RAM]] Unit (RU) | ||
| + | *** 4x 2 KB [[SRAM]] bank | ||
| + | |||
| + | == Memory controller == | ||
| + | {{integrated memory controller | ||
| + | | type = DDR2-400 | ||
| + | | controllers = 2 | ||
| + | | channels = 1 | ||
| + | | ecc support = | ||
| + | | max bandwidth = | ||
| + | | bandwidth schan = | ||
| + | | bandwidth dchan = | ||
| + | | max memory = 4 GiB | ||
| + | }} | ||
| + | |||
| + | == Expansions == | ||
| + | * [[has feature::PCIe]] | ||
| + | * [[has feature::JTAG]] | ||
| + | * 128x [[has feature::GPIO]] @ 100 MHz | ||
| + | * [[has feature::serial flash]] | ||
Latest revision as of 14:16, 13 December 2017
| Edit Values | |
| Am2016 | |
| General Info | |
| Designer | Ambric |
| Model Number | Am2016 |
| Part Number | Am2016 |
| Market | Embedded |
| Introduction | November 15, 2007 (announced) November 15, 2007 (launched) |
| End-of-life | 2012 (last order) 2012 (last shipment) |
| General Specs | |
| Family | Am2000 |
| Series | Gen 2 |
| Locked | No |
| Frequency | 350 MHz |
| Bus speed | 100 MHz |
| Clock multiplier | 3.5 |
| Microarchitecture | |
| Microarchitecture | Ambric |
| Process | 130 nm |
| Technology | CMOS |
| Word Size | 32 bit |
| Cores | 120 |
| Max Memory | 4 GiB |
Am2016 was an MPPA introduced in late 2007 by Ambric. This model was made of roughly 16 Brics arranged as a grid, making up a total of 120 32-bit RICS-like cores operating asynchronously at 1-350 MHz.
Architecture[edit]
- Main article: Am2000 § Architecture
The Am2016 is made of 16 homogeneous 'Brics' laid out in a grid to form 120 cores.
General layout:
- 16x Brics
Memory controller[edit]
| Integrated Memory Controller | |
| Type | DDR2-400 |
| Controllers | 2 |
| Channels | 1 |
| Max memory | 4 GiB |
Expansions[edit]
- PCIe
- JTAG
- 128x GPIO @ 100 MHz
- serial flash
Facts about "Am2016 - Ambric"
| base frequency | 350 MHz (0.35 GHz, 350,000 kHz) + |
| bus speed | 100 MHz (0.1 GHz, 100,000 kHz) + |
| clock multiplier | 3.5 + |
| core count | 120 + |
| designer | Ambric + |
| family | Am2000 + |
| first announced | November 15, 2007 + |
| first launched | November 15, 2007 + |
| full page name | ambric/am2000/am2016 + |
| has feature | PCIe +, JTAG +, GPIO + and serial flash + |
| has locked clock multiplier | false + |
| instance of | microprocessor + |
| last order | 2012 + |
| last shipment | 2012 + |
| ldate | November 15, 2007 + |
| market segment | Embedded + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| microarchitecture | Ambric + |
| model number | Am2016 + |
| name | Am2016 + |
| part number | Am2016 + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| series | Gen 2 + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + |