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Difference between revisions of "intel/xeon e7/e7-4807"
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m (Bot: moving all {{mpu}} to {{chip}})
 
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{{intel title|Xeon E7-4807}}
 
{{intel title|Xeon E7-4807}}
−
{{mpu
+
{{chip
 
| name                = Xeon E7-4807
 
| name                = Xeon E7-4807
 
| no image            = Yes
 
| no image            = Yes
Line 10: Line 10:
 
| model number        = E7-4807
 
| model number        = E7-4807
 
| part number        = AT80615006432AB
 
| part number        = AT80615006432AB
−
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Server
 
| market              = Server
 
| first announced    = April 5, 2011
 
| first announced    = April 5, 2011
Line 18: Line 18:
 
| last order          = August 21, 2015
 
| last order          = August 21, 2015
 
| last shipment      = February 5, 2016
 
| last shipment      = February 5, 2016
 +
| release price      = $890.00
  
 
| family              = Xeon E7
 
| family              = Xeon E7
Line 33: Line 34:
  
 
| microarch          = Westmere
 
| microarch          = Westmere
−
| platform            =  
+
| platform            = Boxboro
 
| chipset            = Boxboro
 
| chipset            = Boxboro
 
| core name          = Westmere EX
 
| core name          = Westmere EX
Line 47: Line 48:
 
| thread count        = 12
 
| thread count        = 12
 
| max cpus            = 4
 
| max cpus            = 4
−
| max memory          = 2,048 GB
+
| max memory          = 2 TiB
 +
 
  
−
| electrical          = Yes
 
 
| v core              = 1.35 V
 
| v core              = 1.35 V
 
| v core tolerance    =  
 
| v core tolerance    =  
Line 67: Line 68:
 
| tstorage max        = 85 °C
 
| tstorage max        = 85 °C
  
−
| packaging          = Yes
+
| package module 1    = {{packages/intel/lga-1567}}
−
| package 0          = FCLGA-8
 
−
| package 0 type      = FCLGA
 
−
| package 0 pins      = 1567
 
−
| package 0 pitch    = 1.016 mm
 
−
| package 0 width    = 49.17 mm
 
−
| package 0 length   = 56.47 mm
 
−
| package 0 height    = 4.484 mm
 
−
| socket 0            = LGA-1567
 
−
| socket 0 type      = LGA
 
 
}}
 
}}
 
'''Xeon E7-4807''' is a {{arch|64}} hexa-core [[x86]] data center microprocessor that supports up to 4 sockets. This first generation ({{intel|Westmere|Westmere}}-based) {{intel|Xeon E7}} processor operates at 1.86 GHz with 95 W TDP but does not support {{intel|turbo boost technology}}. This processor supports up to 4 channels of DDR3, supporting up to 2 TB of memory.
 
'''Xeon E7-4807''' is a {{arch|64}} hexa-core [[x86]] data center microprocessor that supports up to 4 sockets. This first generation ({{intel|Westmere|Westmere}}-based) {{intel|Xeon E7}} processor operates at 1.86 GHz with 95 W TDP but does not support {{intel|turbo boost technology}}. This processor supports up to 4 channels of DDR3, supporting up to 2 TB of memory.
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== Cache ==
 
== Cache ==
 
{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}}
 
{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}}
−
{{cache info
+
{{cache size
−
|l1i cache=192 KB
+
|l1 cache = 384 KiB
−
|l1i break=6x32 KB
+
|l1i cache=192 KiB
 +
|l1i break=6x32 KiB
 
|l1i desc=4-way set associative
 
|l1i desc=4-way set associative
−
|l1i extra=(per core)
+
|l1i policy=write-back
−
|l1d cache=192 KB
+
|l1d cache=192 KiB
−
|l1d break=6x32 KB
+
|l1d break=6x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
−
|l1d extra=(per core)
+
|l1d policy=write-back
−
|l2 cache=1.5 MB
+
|l2 cache=1.5 MiB
−
|l2 break=6x256 KB
+
|l2 break=6x256 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
−
|l2 extra=(per core)
+
|l2 policy=write-back
−
|l3 cache=18 MB
+
|l3 cache=18 MiB
−
|l3 break=
+
|l3 break=6x3 MiB
 
|l3 desc=16-way set associative
 
|l3 desc=16-way set associative
−
|l3 extra=
+
|l3 policy=write-back
 
}}
 
}}
  
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== Memory controller ==
 
== Memory controller ==
−
{{integrated memory controller
+
{{memory controller
−
| type               = DDR3-800
+
|type=DDR3-800
−
| controllers       = 1
+
|ecc=Yes
−
| channels           = 4
+
|max mem=2 TiB
−
| ecc support        = Yes
+
|controllers=1
−
| max bandwidth     =  
+
|channels=4
−
| bandwidth schan    =  
+
|max bandwidth=23.84 GiB/s
−
| bandwidth dchan    =  
+
|bandwidth schan=5.96 GiB/s
−
| max memory        = 2048 GB
+
|bandwidth dchan=11.92 GiB/s
 +
|bandwidth tchan=17.88 GiB/s
 +
|bandwidth qchan=23.84 GiB/s
 
}}
 
}}
  
−
== Features ==  
+
== Features ==
−
{{mpu features
+
{{x86 features
−
| em64t      = Yes
+
|real=Yes
−
| nx          = Yes
+
|protected=Yes
−
| txt        = Yes
+
|smm=Yes
−
| tsx        =  
+
|fpu=Yes
−
| vpro        =  
+
|x8616=Yes
−
| ht          = Yes
+
|x8632=Yes
−
| tbt1        =  
+
|x8664=Yes
−
| tbt2        =  
+
|nx=Yes
−
| bpt        =  
+
|3dnow=No
−
| vt-x        = Yes
+
|e3dnow=No
−
| vt-d        = yes
+
|mmx=Yes
−
| ept        = Yes
+
|emmx=Yes
−
| mmx        = Yes
+
|sse=Yes
−
| sse         = Yes
+
|sse2=Yes
−
| sse2       = Yes
+
|sse3=Yes
−
| sse3       = Yes
+
|ssse3=Yes
−
| ssse3       = Yes
+
|sse41=Yes
−
| sse4.1      = Yes
+
|sse42=Yes
−
| sse4.2      = Yes
+
|sse4a=No
−
| aes        = Yes
+
|avx=No
−
| pclmul      =  
+
|avx2=No
−
| avx        =  
+
 
−
| avx2        =  
+
|abm=No
−
| bmi        =  
+
|tbm=No
−
| bmi1       =  
+
|bmi1=No
−
| bmi2       =  
+
|bmi2=No
−
| f16c       =  
+
|fma3=No
−
| fma3        =  
+
|fma4=No
−
| mpx         =  
+
|aes=Yes
−
| sgx         =  
+
|rdrand=No
−
| eist        = Yes
+
|sha=No
−
| secure key  =  
+
|xop=No
−
| os guard    =  
+
|adx=No
−
| intel at    =  
+
|clmul=No
 +
|f16c=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|flex=No
 +
|fastmem=No
 +
|isrt=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdv=No
 +
|rvi=No
 
}}
 
}}

Latest revision as of 15:28, 13 December 2017

Edit Values
Xeon E7-4807
General Info
DesignerIntel
ManufacturerIntel
Model NumberE7-4807
Part NumberAT80615006432AB
S-SpecSLC3L
MarketServer
IntroductionApril 5, 2011 (announced)
April 5, 2011 (launched)
End-of-lifeAugust 21, 2015 (last order)
February 5, 2016 (last shipment)
Release Price$890.00
ShopAmazon
General Specs
FamilyXeon E7
SeriesE7-4800
LockedYes
Frequency1,866.66 MHz
Bus typeQPI
Bus rate4.80 GT/s
Clock multiplier14
CPUID206F2
Microarchitecture
MicroarchitectureWestmere
PlatformBoxboro
ChipsetBoxboro
Core NameWestmere EX
Core Family6
Core Model47
Core SteppingA2
Process32 nm
Transistors2,600,000,000
TechnologyCMOS
Die513 mm²
Word Size64 bit
Cores6
Threads12
Max Memory2 TiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
Electrical
Vcore1.35 V
TDP95 W
Tcase5 °C – 70 °C
Tstorage-40 °C – 85 °C
Packaging
PackageFCLGA-8 (LGA)FCLGA-8.svg
Dimension49.1 mm x 56.4 mm x 4.2 mm
Pitch1 mm
Pin Count1567
SocketLGA-1567

Xeon E7-4807 is a 64-bit hexa-core x86 data center microprocessor that supports up to 4 sockets. This first generation (Westmere-based) Xeon E7 processor operates at 1.86 GHz with 95 W TDP but does not support turbo boost technology. This processor supports up to 4 channels of DDR3, supporting up to 2 TB of memory.

Cache[edit]

Main article: Westmere § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
393,216 B
0.375 MiB
L1I$192 KiB
196,608 B
0.188 MiB
6x32 KiB4-way set associativewrite-back
L1D$192 KiB
196,608 B
0.188 MiB
6x32 KiB8-way set associativewrite-back
L2$1.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
  6x256 KiB8-way set associativewrite-back
L3$18 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
  6x3 MiB16-way set associativewrite-back

Graphics[edit]

This SoC has no integrated graphics processing unit.

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-800
Supports ECCYes
Max Mem2 TiB
Controllers1
Channels4
Max Bandwidth23.84 GiB/s
24,412.16 MiB/s
25.598 GB/s
25,598.005 MB/s
0.0233 TiB/s
0.0256 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s
Triple 17.88 GiB/s
Quad 23.84 GiB/s

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AESAES Encryption Instructions
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
EISTEnhanced SpeedStep Technology
TXTTrusted Execution Technology (SMX)
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e7/e7-4807&oldid=71031"
Facts about "Xeon E7-4807 - Intel"
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Xeon E7-4807 - Intel#package +
base frequency1,866.66 MHz (1.867 GHz, 1,866,660 kHz) +
bus rate4,800 MT/s (4.8 GT/s, 4,800,000 kT/s) +
bus typeQPI +
chipsetBoxboro +
clock multiplier14 +
core count6 +
core family6 +
core model47 +
core nameWestmere EX +
core steppingA2 +
core voltage1.35 V (13.5 dV, 135 cV, 1,350 mV) +
cpuid206F2 +
designerIntel +
die area513 mm² (0.795 in², 5.13 cm², 513,000,000 µm²) +
familyXeon E7 +
first announcedApril 5, 2011 +
first launchedApril 5, 2011 +
full page nameintel/xeon e7/e7-4807 +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d + and Extended Page Tables +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
l1$ size384 KiB (393,216 B, 0.375 MiB) +
l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description4-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description8-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l3$ description16-way set associative +
l3$ size18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +
last orderAugust 21, 2015 +
last shipmentFebruary 5, 2016 +
ldateApril 5, 2011 +
manufacturerIntel +
market segmentServer +
max case temperature343.15 K (70 °C, 158 °F, 617.67 °R) +
max cpu count4 +
max memory2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) +
max memory channels4 +
max storage temperature358.15 K (85 °C, 185 °F, 644.67 °R) +
microarchitectureWestmere +
min case temperature278.15 K (5 °C, 41 °F, 500.67 °R) +
min storage temperature233.15 K (-40 °C, -40 °F, 419.67 °R) +
model numberE7-4807 +
nameXeon E7-4807 +
packageFCLGA-8 +
part numberAT80615006432AB +
platformBoxboro +
process32 nm (0.032 μm, 3.2e-5 mm) +
release price$ 890.00 (€ 801.00, £ 720.90, ¥ 91,963.70) +
s-specSLC3L +
seriesE7-4800 +
smp max ways4 +
supported memory typeDDR3-800 +
tdp95 W (95,000 mW, 0.127 hp, 0.095 kW) +
technologyCMOS +
thread count12 +
transistor count2,600,000,000 +
word size64 bit (8 octets, 16 nibbles) +