From WikiChip
Difference between revisions of "intel/core i3/i3-6100u"
< intel‎ | core i3

m (Bot: moving all {{mpu}} to {{chip}})
 
(29 intermediate revisions by 4 users not shown)
Line 1: Line 1:
 
{{intel title|Core i3-6100U}}
 
{{intel title|Core i3-6100U}}
−
{{mpu
+
{{chip
−
| name               = Intel Core i3-6100U
+
|name=Core i3-6100U
−
| no image           = Yes
+
|image=skylake u (front; standard).png
−
| image              =
+
|designer=Intel
−
| image size          =
+
|manufacturer=Intel
−
| caption            =  
+
|model number=i3-6100U
−
| designer           = Intel
+
|part number=FJ8066201931104
−
| manufacturer       = Intel
+
|s-spec=SR2EU
−
| model number       = i3-6100U
+
|market=Mobile
−
| part number         = FJ8066201931104
+
|first announced=September 1, 2015
−
| part number 1      =
+
|first launched=September 27, 2015
−
| part number 2      =
+
|release price=$281
−
| part number 3      =
+
|family=Core i3
−
| part number 4      =  
+
|series=i3-6000
−
| market             = Mobile
+
|locked=Yes
−
| first announced     = October 12, 2015
+
|frequency=2,300 MHz
−
| first launched     = October 12, 2015
+
|bus type=OPI
−
| last order          =  
+
|bus rate=4 GT/s
−
| last shipment      =
+
|clock multiplier=23
−
 
+
|isa=x86-64
−
| family             = Core i3
+
|isa family=x86
−
| series             = 6100
+
|microarch=Skylake
−
| locked             = Yes
+
|core name=Skylake U
−
| frequency         = 2300 MHz
+
|core family=6
−
| turbo frequency    =  
+
|core model=78
−
| turbo frequency1  =  
+
|core stepping=D1
−
| turbo frequency2  =  
+
|process=14 nm
−
| turbo frequency3  =  
+
|transistors=1,750,000,000
−
| turbo frequency4  =  
+
|technology=CMOS
−
| bus type          =  
+
|die area=98.57 mm²
−
| bus speed          =  
+
|die length=10.3 mm
−
| clock multiplier  = 23
+
|die width=9.57 mm
−
| s-spec            = SR2EU
+
|mcp=Yes
−
 
+
|die count=2
−
| microarch          = Skylake
+
|word size=64 bit
−
| platform          =  
+
|core count=2
−
| core name          = Skylake U
+
|thread count=4
−
| core stepping      = D1
+
|max cpus=1
−
| process            = 14 nm
+
|max memory=32 GiB
−
| die size          =  
+
|v core min=0.55 V
−
| word size         = 64 bits
+
|v core max=1.52 V
−
| core count         = 2
+
|tdp=15 W
−
| thread count       = 4
+
|ctdp down=7.5 W
−
| max cpus           = 1
+
|ctdp down frequency=800 MHz
−
| max memory         = 32 GB
+
|tjunc min=0 °C
−
 
+
|tjunc max=100 °C
−
| electrical          = Yes
+
|tstorage min=-25 °C
−
| sdp                =  
+
|tstorage max=125 °C
−
| tdp                 = 15 W
+
|package module 1={{packages/intel/fcbga-1356}}
−
| ctdp down           = 7.5 W
 
−
| ctdp down frequency = 800 MHz
 
−
| ctdp up            =
 
−
| ctdp up frequency  =
 
−
| temp max           = 100 °C
 
−
| temp min           = 0 °C
 
−
 
 
−
| packaging          = Yes
 
−
| package           = FCBGA-1356
 
−
| package type      = FCBGA
 
−
| package pitch      = 0.65 mm
 
−
| package size      = 42 mm x 24 mm
 
−
| socket            = BGA-1356
 
−
| socket type        = BGA
 
 
}}
 
}}
−
'''Core i3-6100U''' is a {{arch|64}} [[dual-core]] low-end mobile [[microprocessor]] introduced by [[Intel]] late 2015. This processor, which is based on the {{intel|Skylake}} microarchitecture and manufactured in [[14 nm process]], has a base frequency of 2.3 GHz with a TDP of 15 W with a configurable TDP-down of 7.5 W operating at 800 MHz. This processor incorporates the {{intel|HD Graphics 520}} [[GPU]] clocked at 300 MHz with a max frequency of 1 GHz.
+
'''Core i3-6100U''' is a {{arch|64}} [[dual-core]] entry-level performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 2.3 GHz. The i3-6100U has a TDP of 15 W with a configurable TDP-down of 7.5 W. This chip incorporates the {{intel|HD Graphics 520}} GPU operating at 300 MHz with a burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
  
 
== Cache ==
 
== Cache ==
 
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
−
{{cache info
+
{{cache size
−
|l1i cache=64 KB
+
|l1 cache=128 KiB
−
|l1i break=2x32 KB
+
|l1i cache=64 KiB
 +
|l1i break=2x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
−
|l1i extra=(per core, write-back)
+
|l1d cache=64 KiB
−
|l1d cache=64 KB
+
|l1d break=2x32 KiB
−
|l1d break=2x32 KB
 
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
−
|l1d extra=(per core, write-back)
+
|l1d policy=write-back
−
|l2 cache=512 KB
+
|l2 cache=512 KiB
−
|l2 break=2x256 KB
+
|l2 break=2x256 KiB
 
|l2 desc=4-way set associative
 
|l2 desc=4-way set associative
−
|l2 extra=(per core, write-back)
+
|l2 policy=write-back
−
|l3 cache=3 MB
+
|l3 cache=3 MiB
−
|l3 desc=shared
+
|l3 break=2x1.5 MiB
 +
|l3 policy=write-back
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2133
 +
|type 2=LPDDR3-1866
 +
|type 3=DDR3L-1600
 +
|ecc=No
 +
|max mem=32 GiB
 +
|controllers=1
 +
|channels=2
 +
|max bandwidth=31.79 GiB/s
 +
|bandwidth schan=15.89 GiB/s
 +
|bandwidth dchan=31.79 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 12
 +
| pcie config        = 1x4
 +
| pcie config 2      = 2x2
 +
| pcie config 3      = 1x2+2x1
 +
| pcie config 4      = 4x1
 
}}
 
}}
  
 
== Graphics ==
 
== Graphics ==
−
{{integrated graphic
+
{{integrated graphics
−
| gpu               = Intel HD Graphics 520
+
| gpu                 = HD Graphics 520
−
| device id         = 0x1916
+
| device id           = 0x1916
−
| displays           = 3
+
| designer            = Intel
−
| frequency         = 300 MHz
+
| execution units    = 24
−
| max frequency     = 1 GHz
+
| max displays       = 3
−
| max memory         = 32 GB
+
| max memory          = 32 GiB
−
| output edp         = Yes
+
| frequency           = 300 MHz
−
| output dp         = Yes
+
| max frequency       = 1,000 MHz
−
| output hdmi       = Yes
+
 
−
| output vga         =  
+
| output crt          =
−
| output dvi         = Yes
+
| output sdvo         =  
 +
| output dsi          =
 +
| output edp         = Yes
 +
| output dp           = Yes
 +
| output hdmi         = Yes
 +
| output vga         =  
 +
| output dvi         = Yes
 +
 
 
| directx ver        = 12
 
| directx ver        = 12
 
| opengl ver        = 4.4
 
| opengl ver        = 4.4
Line 112: Line 130:
 
| max res vga        =  
 
| max res vga        =  
 
| max res vga freq  =  
 
| max res vga freq  =  
 +
 +
| features            = Yes
 +
| intel quick sync    = Yes
 +
| intel intru 3d      = Yes
 +
| intel insider        =
 +
| intel widi          =
 +
| intel fdi            =
 +
| intel clear video    = Yes
 +
| intel clear video hd = Yes
 
}}
 
}}
 +
{{skylake hardware accelerated video table|col=1}}
  
−
== Memory controller ==
+
== Features ==  
−
{{integrated memory controller
+
{{x86 features
−
| type              = LPDDR3-1600
+
|real=Yes
−
| type 1            = LPDDR3-1866
+
|protected=Yes
−
| type 2            = DDR4-1866
+
|smm=Yes
−
| type 3            = DDR4-2133
+
|fpu=Yes
−
| controllers        = 1
+
|x8616=Yes
−
| channels          = 2
+
|x8632=Yes
−
| ecc support        = No
+
|x8664=Yes
−
| max bandwidth      = 34,100 MB/s
+
|nx=Yes
−
| max memory        = 32,768 MB
+
|mmx=Yes
−
}}
+
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
  
−
== Expansions ==
+
|abm=Yes
−
{{mpu expansions
+
|tbm=No
−
| pcie revision      = 3.0
+
|bmi1=Yes
−
| pcie lanes        = 12
+
|bmi2=Yes
−
| pcie config        = 1x4
+
|fma3=Yes
−
| pcie config 1      = 2x2
+
|fma4=No
−
| pcie config 2      = 1x2+2x1
+
|aes=Yes
−
| pcie config 3      = 4x1
+
|rdrand=Yes
−
| usb revision      =  
+
|sha=No
−
| usb revision 2    =  
+
|xop=No
−
| usb ports          =  
+
|adx=Yes
−
| sata ports        =  
+
|clmul=Yes
−
| integrated lan    =  
+
|f16c=Yes
−
| uart              =  
+
|tbt1=No
−
| gp io              =  
+
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=Yes
 +
|fastmem=No
 +
|isrt=Yes
 +
|sba=No
 +
|mwt=Yes
 +
|sipp=No
 +
|att=No
 +
|ipt=Yes
 +
|tsx=No
 +
|txt=No
 +
|ht=Yes
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=Yes
 +
|securekey=Yes
 +
|osguard=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 
}}
 
}}

Latest revision as of 15:17, 13 December 2017

Edit Values
Core i3-6100U
skylake u (front; standard).png
General Info
DesignerIntel
ManufacturerIntel
Model Numberi3-6100U
Part NumberFJ8066201931104
S-SpecSR2EU
MarketMobile
IntroductionSeptember 1, 2015 (announced)
September 27, 2015 (launched)
Release Price$281
ShopAmazon
General Specs
FamilyCore i3
Seriesi3-6000
LockedYes
Frequency2,300 MHz
Bus typeOPI
Bus rate4 GT/s
Clock multiplier23
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake
Core NameSkylake U
Core Family6
Core Model78
Core SteppingD1
Process14 nm
Transistors1,750,000,000
TechnologyCMOS
Die98.57 mm²
10.3 mm × 9.57 mm
MCPYes (2 dies)
Word Size64 bit
Cores2
Threads4
Max Memory32 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore0.55 V-1.52 V
TDP15 W
cTDP down7.5 W
cTDP down frequency800 MHz
Tjunction0 °C – 100 °C
Tstorage-25 °C – 125 °C
Packaging
PackageFCBGA-1356 (BGA)
Dimension42 mm x 24 mm x 1.3 mm
Pitch0.65 mm
Ball Count1356
Ball CompSAC405
InterconnectBGA-1356

Core i3-6100U is a 64-bit dual-core entry-level performance x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2.3 GHz. The i3-6100U has a TDP of 15 W with a configurable TDP-down of 7.5 W. This chip incorporates the HD Graphics 520 GPU operating at 300 MHz with a burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
  2x1.5 MiB write-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133, LPDDR3-1866, DDR3L-1600
Supports ECCNo
Max Mem32 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes12
Configs1x4, 2x2, 1x2+2x1, 4x1


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics 520
DesignerIntelDevice ID0x1916
Execution Units24Max Displays3
Max Memory32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
Frequency300 MHz
0.3 GHz
300,000 KHz
Burst Frequency1,000 MHz
1 GHz
1,000,000 KHz
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4096x2304 @24 Hz
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.3
HDMI1.4a
Additional Features
Intel Quick Sync Video
Intel InTru 3D
Intel Clear Video
Intel Clear Video HD

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
EISTEnhanced SpeedStep Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Flex MemoryFlex Memory Access
ISRTSmart Response Technology
MWTMy WiFi Technology
IPTIdentity Protection Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i3/i3-6100u&oldid=70543"
Facts about "Core i3-6100U - Intel"
RDF feed
device id0x1916 +
has featureintegrated gpu +
integrated gpuIntel HD Graphics 520 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu max frequency1,000 MHz (1 GHz, 1,000,000 KHz) +
l1d$ description8-way set associative +
l1i$ description8-way set associative +
l2$ description4-way set associative +
l3$ descriptionshared +