Semiconductor & Computer Engineering
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Difference between revisions of "intel/80486/486dx-50"
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{{intel title|i486DX-50}} | {{intel title|i486DX-50}} | ||
| − | {{ | + | {{chip |
| name = Intel i486DX-50 | | name = Intel i486DX-50 | ||
| − | + | | image = CPU Intel 80486DX-50.JPG | |
| − | | image = | ||
| image size = | | image size = | ||
| − | | caption = | + | | caption = A80486DX-50, S-Spec SX710 |
| designer = Intel | | designer = Intel | ||
| manufacturer = Intel | | manufacturer = Intel | ||
| Line 53: | Line 52: | ||
| core count = 1 | | core count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| + | |||
| − | |||
| power = 4 W | | power = 4 W | ||
| v core = 5 V | | v core = 5 V | ||
| Line 79: | Line 78: | ||
{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1 cache=8 | + | |l1 cache=8 KiB |
| − | |l1 break=1x8 | + | |l1 break=1x8 KiB |
|l1 desc=4-way set associative | |l1 desc=4-way set associative | ||
| − | |l1 extra=(unified, write-through policy ) | + | |l1 extra=(unified, write-through policy) |
}} | }} | ||
| Line 90: | Line 89: | ||
== Features == | == Features == | ||
* {{intel|System Management Mode}} (SMM) | * {{intel|System Management Mode}} (SMM) | ||
| + | |||
| + | == Gallery == | ||
| + | <gallery> | ||
| + | File:Intel i486 DX 50 CPU.jpg|A80486DX-50, S-Spec SX710 | ||
| + | File:Intel i486 dx 50mhz 2007 03 27.jpg|A80486DX-50, S-Spec SX546 | ||
| + | </gallery> | ||
== See also == | == See also == | ||
* {{intel|80486|80486 family}} | * {{intel|80486|80486 family}} | ||
Latest revision as of 15:13, 13 December 2017
| Edit Values | |
| Intel i486DX-50 | |
 | |
| A80486DX-50, S-Spec SX710 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | i486DX-50 |
| Part Number | A80486DX-50 |
| S-Spec | SX408, SX409, SX518, SX546, SX547, SX705, SX710, SXE69 Q0209 (QS), Q302 (QS) |
| Introduction | June 24, 1991 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | 80486 |
| Series | 486DX |
| Frequency | 50 MHz |
| Bus type | FSB |
| Bus speed | 50 MHz |
| Bus rate | 50 MT/s |
| Clock multiplier | 1 |
| CPUID | 411, 413 |
| Microarchitecture | |
| Microarchitecture | 80486 |
| Core Name | 486DX |
| Process | 1 µm, 800 nm |
| Transistors | 1,200,000 |
| Technology | CMOS |
| Word Size | 32 bit |
| Cores | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 4 W |
| Vcore | 5 V ± 5% |
| OP Temperature | 0 °C – 85 °C |
i486DX-50 was a fourth-generation x86 microprocessor introduced by Intel in 1991. This chip, which is based on the 80486 microarchitecture, operated at 50 MHz. This chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM).
Contents
Cache[edit]
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative (unified, write-through policy) |
Graphics[edit]
This chip had no integrated graphics processing unit.
Features[edit]
- System Management Mode (SMM)
Gallery[edit]
A80486DX-50, S-Spec SX710
A80486DX-50, S-Spec SX546
