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Difference between revisions of "intel/core m/5y51"
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(→‎Memory controller)
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{{title|Core M 5Y51}}
 
{{title|Core M 5Y51}}
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{{mpu
+
{{chip
 
| name                = Core M 5Y51
 
| name                = Core M 5Y51
 
| no image            = Yes
 
| no image            = Yes
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| cpuid              =  
 
| cpuid              =  
  
 +
| isa family          = x86
 +
| isa                = x86-64
 
| microarch          = Broadwell
 
| microarch          = Broadwell
 
| platform            =  
 
| platform            =  
 
| chipset            =  
 
| chipset            =  
 
| core name          = Broadwell Y
 
| core name          = Broadwell Y
−
| core family        =  
+
| core family        = 06
−
| core model          =  
+
| core model          = 3D
 
| core stepping      = F0
 
| core stepping      = F0
 
| process            = 14 nm
 
| process            = 14 nm
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| thread count        = 4
 
| thread count        = 4
 
| max cpus            = 1
 
| max cpus            = 1
−
| max memory          = 16 GB
+
| max memory          = 16 GiB
 +
 
  
−
| electrical          = Yes
 
 
| v core              =  
 
| v core              =  
 
| v core tolerance    =  
 
| v core tolerance    =  
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{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
 
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
 
{{cache info
 
{{cache info
−
|l1i cache=64 KB
+
|l1i cache=64 KiB
−
|l1i break=2x32 KB
+
|l1i break=2x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
 
|l1i extra=(per core)
 
|l1i extra=(per core)
−
|l1d cache=64 KB
+
|l1d cache=64 KiB
−
|l1d break=2x32 KB
+
|l1d break=2x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d extra=(per core)
 
|l1d extra=(per core)
−
|l2 cache=512 MB
+
|l2 cache=512 MiB
−
|l2 break=2x256 KB
+
|l2 break=2x256 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l2 extra=(per core)
 
|l2 extra=(per core)
−
|l3 cache=4 MB
+
|l3 cache=4 MiB
−
|l3 break=2x2 MB
+
|l3 break=2x2 MiB
−
|l3 desc=
 
 
|l3 extra=(shared LLC)
 
|l3 extra=(shared LLC)
 
}}
 
}}
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| frequency          = 300 MHz
 
| frequency          = 300 MHz
 
| max frequency      = 900 MHz
 
| max frequency      = 900 MHz
−
| max memory          = 16 GB
+
| max memory          = 16 GiB
  
 
| output crt          =  
 
| output crt          =  
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== Expansions ==
 
== Expansions ==
−
{{mpu expansions
+
{{expansions
 
| pcie revision      = 2.0
 
| pcie revision      = 2.0
 
| pcie lanes        = 12
 
| pcie lanes        = 12
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== Features ==  
 
== Features ==  
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{{mpu features
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{{x86 features
 
| em64t      = Yes
 
| em64t      = Yes
 
| nx          = Yes
 
| nx          = Yes

Latest revision as of 15:24, 13 December 2017

Edit Values
Core M 5Y51
General Info
DesignerIntel
ManufacturerIntel
Model Number5Y51
Part NumberFH8065802061802
S-SpecSR23L
MarketMobile
IntroductionNovember, 2014 (announced)
January, 2015 (launched)
ShopAmazon
General Specs
FamilyCore M
Series5000
LockedYes
Frequency1100 MHz
Turbo FrequencyYes
Turbo Frequency2600 MHz (1 core)
Bus typeDMI 2.0
Clock multiplier11
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureBroadwell
Core NameBroadwell Y
Core Family06
Core Model3D
Core SteppingF0
Process14 nm
Transistors1,300,000,000
TechnologyCMOS
Die82 mm²
Word Size64 bit
Cores2
Threads4
Max Memory16 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
SDP3.5 W
TDP4.5 W
cTDP down3.5 W
cTDP down frequency600 MHz
cTDP up6 W
cTDP up frequency1.3 GHz
OP Temperature0 °C – 95 °C

The Core M 5Y51 is an ultra-low power dual-core 64-bit x86 microprocessor introduced by Intel in 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.6 GHz. The 5Y51 has a configurable TDP-down of 3.5 W @ 600 MHz and a configurable TDP-up of 6 W @ 1.3 GHz. This chip, which is manufactured in 14 nm process based on the Broadwell microarchitecture and incorporates Intel's HD Graphics 5300 Gen8 GPU clocked at 300 MHz with turbo frequency of 900 MHz.

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core)
L1D$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core)
L2$ 512 MiB
524,288 KiB
536,870,912 B
0.5 GiB
2x256 KiB 8-way set associative (per core)
L3$ 4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
2x2 MiB (shared LLC)

Graphics[edit]

Integrated Graphic Information
GPU Intel HD Graphics 5300
Device ID 0x161E
Execution Units 24
Displays 3
Frequency 300 MHz
0.3 GHz
300,000 KHz
Max frequency 900 MHz
0.9 GHz
900,000 KHz
Max memory 16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
Output DisplayPort, Embedded DisplayPort, HDMI
DirectX 11.2
OpenGL 4.3
OpenCL 2.0
HDMI 1.4a
DP 1.2
eDP 1.3
Max HDMI Res 2560x1600 @60 Hz, 4096x2304 @24 Hz
Max DVI Res 1920x1200 @60 Hz
Max DP Res 2560x1600 @60 Hz, 3840x2160 @60 Hz
Max eDP Res 2560x1600 @60 Hz, 3840x2160 @60 Hz
Intel Quick Sync Video
Intel InTru 3D
Intel Insider
Intel WiDi (Wireless Display)
Intel Flexible Display Interface (FDI)
Intel Clear Video
  • AVC/H.264 Encode
  • MPEG2 Encode
  • MVC HW Encode
  • JPEG/MJPEG Hardware Encode
  • Blu-ray* Disc Playback
  • AVC/H.264, MPEG2, VC1 Decode

Memory controller[edit]

Integrated Memory Controller
Type LPDDR3-1333, LPDDR3-1600, DDR3L-1600, DDR3L-RS1600
Controllers 1
Channels 2
ECC Support No
Max bandwidth 25.6 GB/s
Max memory 16 GB

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes12
Configs6x1, 3x4


Features[edit]

Drivers[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_m/5y51&oldid=70841"
Facts about "Core M 5Y51"
RDF feed
device id0x161E +
drivers urlhttps://downloadcenter.intel.com/product/94028 +
has featureintegrated gpu +
integrated gpuIntel HD Graphics 5300 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu max frequency900 MHz (0.9 GHz, 900,000 KHz) +
l1d$ description8-way set associative +
l1i$ description8-way set associative +
l2$ description8-way set associative +