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Difference between revisions of "intel/xeon d/d-1529"
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{{intel title|Xeon D-1529}} | {{intel title|Xeon D-1529}} | ||
− | {{ | + | {{chip |
− | | name | + | |name=Xeon D-1529 |
− | | image | + | |image=broadwell de (front).png |
− | | image | + | |back image=broadwell de (back).png |
− | | | + | |designer=Intel |
− | + | |manufacturer=Intel | |
− | | manufacturer | + | |model number=D-1529 |
− | | model number | + | |part number=GG8067402570001 |
− | | part number | + | |s-spec=SR2DR |
− | | market | + | |market=Server |
− | | first announced | + | |market 2=Embedded |
− | | first launched | + | |first announced=April, 2016 |
− | | | + | |first launched=April, 2016 |
− | | | + | |release price (tray)=$266.00 |
+ | |family=Xeon D | ||
+ | |series=D-1500 | ||
+ | |locked=Yes | ||
+ | |frequency=1,300 MHz | ||
+ | |bus type=DMI 2.0 | ||
+ | |clock multiplier=13 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Broadwell | ||
+ | |platform=Grangeville | ||
+ | |core name=Broadwell DE | ||
+ | |core family=6 | ||
+ | |core model=6 | ||
+ | |core stepping=V2 | ||
+ | |process=14 nm | ||
+ | |transistors=3,200,000,000 | ||
+ | |technology=CMOS | ||
+ | |die area=246.24 mm² | ||
+ | |word size=64 bit | ||
+ | |core count=4 | ||
+ | |thread count=8 | ||
+ | |max cpus=1 | ||
+ | |max memory=128 GiB | ||
+ | |tdp=20 W | ||
+ | |temp min=-40 °C | ||
+ | |temp max=85 °C | ||
+ | |package name 1=intel,fcbga_1667 | ||
+ | }} | ||
+ | '''Xeon D-1529''' is a {{arch|64}} [[quad-core]] [[x86]] microserver SoC introduced by [[Intel]] in early [[2016]]. The D-1529 is based on the {{intel|Broadwell|l=arch}} microarchitecture and is fabricated on their [[14 nm process]]. It operates at 1.3 GHz with a TDP of 20 W supporting up to 128 GiB of dual-channel DDR4-1600 memory. | ||
+ | |||
+ | The D-1529 is a special model that's {{iec|61508|IEC-61508}} ([[safety integrity level]] 2) certified for use in safety-critical systems. The D-1529 is supported by VxWorks, Wind River Linux and Wind River Simics. | ||
− | | | + | == Cache == |
− | | | + | {{main|intel/microarchitectures/broadwell (server)#Memory_Hierarchy|l1=Broadwell § Cache}} |
− | | | + | {{cache size |
− | | | + | |l1 cache=256 KiB |
− | | | + | |l1i cache=128 KiB |
− | | | + | |l1i break=4x32 KiB |
− | | | + | |l1i desc=8-way set associative |
− | | | + | |l1d cache=128 KiB |
− | | | + | |l1d break=4x32 KiB |
− | | | + | |l1d desc=8-way set associative |
− | | | + | |l1d policy=write-back |
− | | | + | |l2 cache=1 MiB |
− | | | + | |l2 break=4x256 KiB |
− | | | + | |l2 desc=8-way set associative |
− | | | + | |l2 policy=write-back |
− | | | + | |l3 cache=6 MiB |
+ | |l3 break=4x1.5 MiB | ||
+ | |l3 desc=16-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
− | + | == Graphics == | |
− | + | This SoC has no integrated graphics processing unit. | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | | | + | == Memory controller == |
− | | | + | {{memory controller |
− | | | + | |type=DDR4-1600 |
− | | | + | |ecc=Yes |
− | | | + | |max mem=128 GiB |
− | | | + | |controllers=1 |
− | | | + | |channels=2 |
− | | | + | |max bandwidth=23.84 GiB/s |
+ | |bandwidth schan=11.92 GiB/s | ||
+ | |bandwidth dchan=23.84 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=24 | ||
+ | |pcie config=x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=2.0 | ||
+ | |pcie lanes=8 | ||
+ | |pcie config=x8 | ||
+ | |pcie config 2=x4 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=USB | ||
+ | |usb revision=3.0 | ||
+ | |usb ports=4 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=USB | ||
+ | |usb revision=2.0 | ||
+ | |usb ports=4 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=SATA | ||
+ | |sata revision=3 | ||
+ | |sata ports=6 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | == Networking == | ||
+ | {{network | ||
+ | |eth opts=Yes | ||
+ | |10ge=Yes | ||
+ | |10ge ports=2 | ||
+ | }} | ||
− | | | + | == Features == |
− | | | + | {{x86 features |
− | | | + | |real=Yes |
− | | | + | |protected=Yes |
− | | | + | |smm=Yes |
− | | | + | |fpu=Yes |
− | | | + | |x8616=Yes |
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=No | ||
+ | |avx512cd=No | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=No | ||
+ | |avx512dq=No | ||
+ | |avx512vl=No | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx512vnni=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |bfloat16=No | ||
+ | |tbt1=No | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=No | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=No | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=No | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=Yes | ||
+ | |osguard=Yes | ||
+ | |intqat=No | ||
+ | |dlboost=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
+ | |em64t=Yes | ||
+ | |vt-x=Yes | ||
+ | |vt-d=Yes | ||
+ | |sse4=Yes | ||
+ | |sse4_1=Yes | ||
+ | |sse4_2=Yes | ||
+ | |bmi=Yes | ||
+ | |secure key=Yes | ||
+ | |os guard=Yes | ||
}} | }} | ||
− |
Latest revision as of 01:20, 1 April 2019
Edit Values | |
Xeon D-1529 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | D-1529 |
Part Number | GG8067402570001 |
S-Spec | SR2DR |
Market | Server, Embedded |
Introduction | April, 2016 (announced) April, 2016 (launched) |
Release Price | $266.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon D |
Series | D-1500 |
Locked | Yes |
Frequency | 1,300 MHz |
Bus type | DMI 2.0 |
Clock multiplier | 13 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Broadwell |
Platform | Grangeville |
Core Name | Broadwell DE |
Core Family | 6 |
Core Model | 6 |
Core Stepping | V2 |
Process | 14 nm |
Transistors | 3,200,000,000 |
Technology | CMOS |
Die | 246.24 mm² |
Word Size | 64 bit |
Cores | 4 |
Threads | 8 |
Max Memory | 128 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 20 W |
OP Temperature | -40 °C – 85 °C |
Packaging | |
Package | FCBGA-1667 (FCBGA) |
Dimension | 37.5 mm × 37.5 mm × 3.557 mm |
Pitch | 0.7 mm |
Contacts | 1667 |
Xeon D-1529 is a 64-bit quad-core x86 microserver SoC introduced by Intel in early 2016. The D-1529 is based on the Broadwell microarchitecture and is fabricated on their 14 nm process. It operates at 1.3 GHz with a TDP of 20 W supporting up to 128 GiB of dual-channel DDR4-1600 memory.
The D-1529 is a special model that's IEC-61508 (safety integrity level 2) certified for use in safety-critical systems. The D-1529 is supported by VxWorks, Wind River Linux and Wind River Simics.
Cache[edit]
- Main article: Broadwell § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics[edit]
This SoC has no integrated graphics processing unit.
Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options |
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Networking[edit]
Networking
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Features[edit]
[Edit/Modify Supported Features]
Facts about "Xeon D-1529 - Intel"
l1d$ description | 8-way set associative + |
l1i$ description | 8-way set associative + |
l2$ description | 8-way set associative + |