Semiconductor & Computer Engineering
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<pre> | <pre> | ||
{{microarchitecture | {{microarchitecture | ||
| + | | atype = "CPU" or "GPU" (meta-related) | ||
| name = | | name = | ||
| + | | designer = | ||
| manufacturer = | | manufacturer = | ||
| introduction = | | introduction = | ||
| Line 11: | Line 13: | ||
| cores N = | | cores N = | ||
| − | |||
| type = <!-- e.g. "Superscalar" --> | | type = <!-- e.g. "Superscalar" --> | ||
| type 2 = | | type 2 = | ||
| type N = | | type N = | ||
| − | | | + | | oooe = <!-- Yes or No only --> |
| speculative = <!-- Yes or No only --> | | speculative = <!-- Yes or No only --> | ||
| renaming = <!-- Yes or No only --> | | renaming = <!-- Yes or No only --> | ||
| + | | stages = <!-- ONLY IF FIXED SIZE, otherwise use below for range --> | ||
| + | | stages min = | ||
| + | | stages max = | ||
| + | | decode = 2-way | ||
| + | |||
| isa = | | isa = | ||
| isa 2 = | | isa 2 = | ||
| isa N = | | isa N = | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| feature = | | feature = | ||
| extension = | | extension = | ||
| Line 32: | Line 32: | ||
| extension N = | | extension N = | ||
| − | |||
| l1i = | | l1i = | ||
| l1i per = | | l1i per = | ||
| Line 40: | Line 39: | ||
| l1d desc = | | l1d desc = | ||
| l2 = | | l2 = | ||
| − | | l2 | + | | l2 per = |
| − | | | + | | l2 desc = |
| + | | l3 = | ||
| + | | l3 per = | ||
| + | | l3 desc = | ||
| − | |||
| core name = | | core name = | ||
| core name 2 = | | core name 2 = | ||
| core name N = | | core name N = | ||
| − | | | + | | predecessor = |
| − | | predecessor = | + | | predecessor link = |
| − | | | + | | successor = |
| − | | successor | + | | successor link = |
| − | | successor link | + | | successor 2 = |
| + | | successor 2 link = | ||
| + | | successor N = | ||
| + | | successor N link = | ||
}} | }} | ||
</pre> | </pre> | ||
Latest revision as of 17:31, 25 May 2017
Code[edit]
{{microarchitecture
| atype = "CPU" or "GPU" (meta-related)
| name =
| designer =
| manufacturer =
| introduction =
| phase-out =
| process =
| cores =
| cores 2 =
| cores N =
| type = <!-- e.g. "Superscalar" -->
| type 2 =
| type N =
| oooe = <!-- Yes or No only -->
| speculative = <!-- Yes or No only -->
| renaming = <!-- Yes or No only -->
| stages = <!-- ONLY IF FIXED SIZE, otherwise use below for range -->
| stages min =
| stages max =
| decode = 2-way
| isa =
| isa 2 =
| isa N =
| feature =
| extension =
| extension 2 =
| extension N =
| l1i =
| l1i per =
| l1i desc =
| l1d =
| l1d per =
| l1d desc =
| l2 =
| l2 per =
| l2 desc =
| l3 =
| l3 per =
| l3 desc =
| core name =
| core name 2 =
| core name N =
| predecessor =
| predecessor link =
| successor =
| successor link =
| successor 2 =
| successor 2 link =
| successor N =
| successor N link =
}}