From WikiChip
Difference between revisions of "intel/atom x5/x5-z8500"
m (→Cache) |
m (Bot: moving all {{mpu}} to {{chip}}) |
||
(8 intermediate revisions by 3 users not shown) | |||
Line 1: | Line 1: | ||
{{intel title|Atom x5-Z8500}} | {{intel title|Atom x5-Z8500}} | ||
− | {{ | + | {{chip |
| name = Intel Atom x5-Z8500 | | name = Intel Atom x5-Z8500 | ||
| no image = Yes | | no image = Yes | ||
Line 6: | Line 6: | ||
| image size = | | image size = | ||
| caption = | | caption = | ||
+ | | designer = Intel | ||
| manufacturer = Intel | | manufacturer = Intel | ||
| model number = x5-Z8500 | | model number = x5-Z8500 | ||
Line 42: | Line 43: | ||
| thread count = 4 | | thread count = 4 | ||
| max cpus = 1 | | max cpus = 1 | ||
− | | max memory = 8 | + | | max memory = 8 GiB |
| max memory addr = | | max memory addr = | ||
− | + | ||
| power = | | power = | ||
| sdp = 2 W | | sdp = 2 W | ||
Line 63: | Line 64: | ||
| socket type = BGA | | socket type = BGA | ||
}} | }} | ||
− | The '''Atom x5-Z8500''' is a {{arch|64}} quad-core [[system on a chip]] introduce by [[Intel]] in early 2015. This ultra-low power SoC has a scenario design power of 2 W and operates at a base frequency of 1.44 GHz with a burst up to 2.24 GHz and supports up to 8 | + | The '''Atom x5-Z8500''' is a {{arch|64}} quad-core [[system on a chip]] introduce by [[Intel]] in early 2015. This ultra-low power SoC has a scenario design power of 2 W and operates at a base frequency of 1.44 GHz with a burst up to 2.24 GHz and supports up to 8 GiB of memory. This chip incorporates the {{intel|HD Graphics (Cherry Trail)}} GPU. |
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/airmont#Memory_Hierarchy|l1=Airmont | + | {{main|intel/microarchitectures/airmont#Memory_Hierarchy|l1=Airmont § Cache}} |
{{cache info | {{cache info | ||
− | |l1i cache=128 | + | |l1i cache=128 KiB |
− | |l1i break=4x32 | + | |l1i break=4x32 KiB |
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
|l1i extra=(per core) | |l1i extra=(per core) | ||
− | |l1d cache=96 | + | |l1d cache=96 KiB |
− | |l1d break=4x24 | + | |l1d break=4x24 KiB |
|l1d desc=6-way set associative | |l1d desc=6-way set associative | ||
|l1d extra=(per core) | |l1d extra=(per core) | ||
− | |l2 cache=2 | + | |l2 cache=2 MiB |
− | |l2 break=2x1 | + | |l2 break=2x1 MiB |
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
|l2 extra=(per 2 cores) | |l2 extra=(per 2 cores) | ||
− | |l3 cache=0 | + | |l3 cache=0 KiB |
|l3 desc=No L3$ | |l3 desc=No L3$ | ||
}} | }} | ||
Line 103: | Line 104: | ||
| frequency = 200 MHz | | frequency = 200 MHz | ||
| max frequency = 600 MHz | | max frequency = 600 MHz | ||
− | | max memory = 8 | + | | max memory = 8 GiB |
| output edp = Yes | | output edp = Yes | ||
| output dp = | | output dp = | ||
Line 139: | Line 140: | ||
== Expansions == | == Expansions == | ||
− | {{ | + | {{expansions |
| pcie revision = 2.0 | | pcie revision = 2.0 | ||
| pcie lanes = 2 | | pcie lanes = 2 | ||
Line 147: | Line 148: | ||
== Features == | == Features == | ||
− | {{ | + | {{x86 features |
| em64t = Yes | | em64t = Yes | ||
| nx = Yes | | nx = Yes |
Latest revision as of 16:15, 13 December 2017
Edit Values | |
Intel Atom x5-Z8500 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | x5-Z8500 |
Part Number | FJ8066401715814, FJ8066401715842 |
S-Spec | SR27N, SR2GN |
Market | Mobile |
Introduction | March 2, 2015 (announced) March 2, 2015 (launched) |
Shop | Amazon |
General Specs | |
Family | Atom x5 |
Series | Z8000 |
Locked | Yes |
Frequency | 1440 MHz |
Turbo Frequency | Yes |
Turbo Frequency | 2240 MHz (1 core) |
Microarchitecture | |
Microarchitecture | Airmont |
Platform | Cherry Trail |
Core Name | Cherry Trail |
Core Stepping | C0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 4 |
Threads | 4 |
Max Memory | 8 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
SDP | 2 W |
OP Temperature | 0 °C – 90 °C |
The Atom x5-Z8500 is a 64-bit quad-core system on a chip introduce by Intel in early 2015. This ultra-low power SoC has a scenario design power of 2 W and operates at a base frequency of 1.44 GHz with a burst up to 2.24 GHz and supports up to 8 GiB of memory. This chip incorporates the HD Graphics (Cherry Trail) GPU.
Cache[edit]
- Main article: Airmont § Cache
Cache Info [Edit Values] | ||
L1I$ | 128 KiB 131,072 B 0.125 MiB |
4x32 KiB 8-way set associative (per core) |
L1D$ | 96 KiB 98,304 B 0.0938 MiB |
4x24 KiB 6-way set associative (per core) |
L2$ | 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB |
2x1 MiB 16-way set associative (per 2 cores) |
L3$ | 0 KiB 0 MiB 0 B 0 GiB |
No L3$ |
Memory controller[edit]
Integrated Memory Controller | |
Type | DDR3L-RS 1600, LPDDR3 1600 |
Controllers | 1 |
Channels | 2 |
ECC Support | Yes |
Bandwidth (single) | 12,800 MB/s |
Bandwidth (dual) | 25,600 MB/s |
Max memory | 8,192 MB |
Graphics[edit]
Integrated Graphic Information | |
GPU | HD Graphics (Cherry Trail) |
Execution Units | 12 |
Displays | 3 |
Frequency | 200 MHz 0.2 GHz
200,000 KHz |
Max frequency | 600 MHz 0.6 GHz
600,000 KHz |
Max memory | 8 GiB 8,192 MiB
8,388,608 KiB 8,589,934,592 B |
Output | Embedded DisplayPort, HDMI |
DirectX | 11.1 |
OpenGL | 4.3 |
OpenCL | 1.2 |
OpenGL ES | 3.0 |
DVI | 1.4b |
HDMI | 1.4b |
DVI | 1.4b |
Vulkan | 1.0 |
DP | 1.1a |
eDP | 1.3 |
Max HDMI Res | 3840x2160 @60 |
Max DVI Res | 3840x2160 @60 Hz |
Max DSI Res | 2560x1600 @60 Hz |
Max DP Res | 2560x1600 @60 |
Max eDP Res | 2560x1600 @60 Hz |
- Video decode hardware acceleration including support for H.263, MPEG4, H.264, H.265 (HEVC), VP8, VP9, MVC, MPEG2, VC1, JPEG.
- Video encode hardware acceleration including support for H.264, H.263, VP8, MVC, JPEG.
- Four planes available per pipe - 1x Primary, 2x Video Sprite & 1x Cursor.
- Two dedicated digital Display Serial Interface PHYs implementing MIPI-DSI support.
Expansions[edit]
![]() |
Expansion Options
|
|||||||
|
Features[edit]
[Edit/Modify Supported Features]
![]() |
Supported x86 Extensions & Processor Features
|
|||||||||||||||||
|
Storage[edit]
- SD Card support (x1 SDR104)
- SDIO support (x1 SDR104)
- eMMC support (4.51)
Audio[edit]
- Low Power Engine (3 I2S ports)
Package[edit]
Property | Value |
---|---|
Type | 17x17mm Type 4 |
IO count | 628 |
Ball count | 1380 |
Ball pitch | 0.4mm |
Z-height | 0.937mm |
Facts about "Atom x5-Z8500 - Intel"
has feature | integrated gpu +, SD Card support +, SDIO support +, eMMC support + and Low Power Engine + |
integrated gpu | HD Graphics (Cherry Trail) + |
integrated gpu base frequency | 200 MHz (0.2 GHz, 200,000 KHz) + |
integrated gpu max frequency | 600 MHz (0.6 GHz, 600,000 KHz) + |
l1d$ description | 6-way set associative + |
l1i$ description | 8-way set associative + |
l2$ description | 16-way set associative + |
l3$ description | No L3$ + |
l3$ size | 0 MiB (0 KiB, 0 B, 0 GiB) + |