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Difference between revisions of "intel/atom x5/x5-z8500"
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{{intel title|Atom x5-Z8500}}
 
{{intel title|Atom x5-Z8500}}
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{{mpu
+
{{chip
 
| name                = Intel Atom x5-Z8500
 
| name                = Intel Atom x5-Z8500
 
| no image            = Yes
 
| no image            = Yes
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| image size          =  
 
| image size          =  
 
| caption            =  
 
| caption            =  
 +
| designer            = Intel
 
| manufacturer        = Intel
 
| manufacturer        = Intel
 
| model number        = x5-Z8500
 
| model number        = x5-Z8500
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| thread count        = 4
 
| thread count        = 4
 
| max cpus            = 1
 
| max cpus            = 1
−
| max memory          = 8 GB
+
| max memory          = 8 GiB
 
| max memory addr    =  
 
| max memory addr    =  
  
−
| electrical          = Yes
+
 
 
| power              =  
 
| power              =  
 
| sdp                = 2 W
 
| sdp                = 2 W
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| socket type        = BGA
 
| socket type        = BGA
 
}}
 
}}
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The '''Atom x5-Z8500''' is a {{arch|64}} quad-core [[system on a chip]] introduce by [[Intel]] in early 2015. This ultra-low power SoC has a scenario design power of 2 W and operates at a base frequency of 1.44 GHz with a burst up to 2.24 GHz and supports up to 8 GB of memory. This chip incorporates the {{intel|HD Graphics (Cherry Trail)}} GPU.
+
The '''Atom x5-Z8500''' is a {{arch|64}} quad-core [[system on a chip]] introduce by [[Intel]] in early 2015. This ultra-low power SoC has a scenario design power of 2 W and operates at a base frequency of 1.44 GHz with a burst up to 2.24 GHz and supports up to 8 GiB of memory. This chip incorporates the {{intel|HD Graphics (Cherry Trail)}} GPU.
  
 
== Cache ==
 
== Cache ==
 +
{{main|intel/microarchitectures/airmont#Memory_Hierarchy|l1=Airmont § Cache}}
 
{{cache info
 
{{cache info
−
|l1i cache=128 KB
+
|l1i cache=128 KiB
−
|l1i break=4x32 KB
+
|l1i break=4x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
 
|l1i extra=(per core)
 
|l1i extra=(per core)
−
|l1d cache=96 KB
+
|l1d cache=96 KiB
−
|l1d break=4x24 KB
+
|l1d break=4x24 KiB
 
|l1d desc=6-way set associative
 
|l1d desc=6-way set associative
 
|l1d extra=(per core)
 
|l1d extra=(per core)
−
|l2 cache=1 MB
+
|l2 cache=2 MiB
−
|l2 break=2x1 MB
+
|l2 break=2x1 MiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
−
|l2 extra=(per core 2 cores)
+
|l2 extra=(per 2 cores)
−
|l3 cache=0 KB
+
|l3 cache=0 KiB
 
|l3 desc=No L3$
 
|l3 desc=No L3$
 
}}
 
}}
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| frequency          = 200 MHz
 
| frequency          = 200 MHz
 
| max frequency      = 600 MHz
 
| max frequency      = 600 MHz
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| max memory          = 8 GB
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| max memory          = 8 GiB
 
| output edp          = Yes
 
| output edp          = Yes
 
| output dp          =  
 
| output dp          =  
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== Expansions ==
 
== Expansions ==
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{{mpu expansions
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{{expansions
 
| pcie revision      = 2.0
 
| pcie revision      = 2.0
 
| pcie lanes        = 2
 
| pcie lanes        = 2
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== Features ==
 
== Features ==
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{{mpu features
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{{x86 features
 
| em64t    = Yes
 
| em64t    = Yes
 
| nx        = Yes
 
| nx        = Yes

Latest revision as of 15:15, 13 December 2017

Edit Values
Intel Atom x5-Z8500
General Info
DesignerIntel
ManufacturerIntel
Model Numberx5-Z8500
Part NumberFJ8066401715814,
FJ8066401715842
S-SpecSR27N, SR2GN
MarketMobile
IntroductionMarch 2, 2015 (announced)
March 2, 2015 (launched)
ShopAmazon
General Specs
FamilyAtom x5
SeriesZ8000
LockedYes
Frequency1440 MHz
Turbo FrequencyYes
Turbo Frequency2240 MHz (1 core)
Microarchitecture
MicroarchitectureAirmont
PlatformCherry Trail
Core NameCherry Trail
Core SteppingC0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads4
Max Memory8 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
SDP2 W
OP Temperature0 °C – 90 °C

The Atom x5-Z8500 is a 64-bit quad-core system on a chip introduce by Intel in early 2015. This ultra-low power SoC has a scenario design power of 2 W and operates at a base frequency of 1.44 GHz with a burst up to 2.24 GHz and supports up to 8 GiB of memory. This chip incorporates the HD Graphics (Cherry Trail) GPU.

Cache[edit]

Main article: Airmont § Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core)
L1D$ 96 KiB
98,304 B
0.0938 MiB
4x24 KiB 6-way set associative (per core)
L2$ 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
2x1 MiB 16-way set associative (per 2 cores)
L3$ 0 KiB
0 MiB
0 B
0 GiB
No L3$

Memory controller[edit]

Integrated Memory Controller
Type DDR3L-RS 1600, LPDDR3 1600
Controllers 1
Channels 2
ECC Support Yes
Bandwidth (single) 12,800 MB/s
Bandwidth (dual) 25,600 MB/s
Max memory 8,192 MB

Graphics[edit]

Integrated Graphic Information
GPU HD Graphics (Cherry Trail)
Execution Units 12
Displays 3
Frequency 200 MHz
0.2 GHz
200,000 KHz
Max frequency 600 MHz
0.6 GHz
600,000 KHz
Max memory 8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
Output Embedded DisplayPort, HDMI
DirectX 11.1
OpenGL 4.3
OpenCL 1.2
OpenGL ES 3.0
DVI 1.4b
HDMI 1.4b
DVI 1.4b
Vulkan 1.0
DP 1.1a
eDP 1.3
Max HDMI Res 3840x2160 @60
Max DVI Res 3840x2160 @60 Hz
Max DSI Res 2560x1600 @60 Hz
Max DP Res 2560x1600 @60
Max eDP Res 2560x1600 @60 Hz
  • Video decode hardware acceleration including support for H.263, MPEG4, H.264, H.265 (HEVC), VP8, VP9, MVC, MPEG2, VC1, JPEG.
  • Video encode hardware acceleration including support for H.264, H.263, VP8, MVC, JPEG.
  • Four planes available per pipe - 1x Primary, 2x Video Sprite & 1x Cursor.
  • Two dedicated digital Display Serial Interface PHYs implementing MIPI-DSI support.

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes2
Configs1x2


Features[edit]

Storage[edit]

  • SD Card support (x1 SDR104)
  • SDIO support (x1 SDR104)
  • eMMC support (4.51)

Audio[edit]

  • Low Power Engine (3 I2S ports)

Package[edit]

Property Value
Type 17x17mm Type 4
IO count 628
Ball count 1380
Ball pitch 0.4mm
Z-height 0.937mm
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/atom_x5/x5-z8500&oldid=70428"
Facts about "Atom x5-Z8500 - Intel"
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Atom x5-Z8500 - Intel#io +
base frequency1,440 MHz (1.44 GHz, 1,440,000 kHz) +
core count4 +
core nameCherry Trail +
core steppingC0 +
designerIntel +
familyAtom x5 +
first announcedMarch 2, 2015 +
first launchedMarch 2, 2015 +
full page nameintel/atom x5/x5-z8500 +
has featureintegrated gpu +, Advanced Encryption Standard Instruction Set Extension +, Burst Performance Technology +, Enhanced SpeedStep Technology +, SD Card support +, SDIO support +, eMMC support + and Low Power Engine +
has intel burst performance technologytrue +
has intel enhanced speedstep technologytrue +
has locked clock multipliertrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpuHD Graphics (Cherry Trail) +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu max frequency600 MHz (0.6 GHz, 600,000 KHz) +
integrated gpu max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB) +
l1d$ description6-way set associative +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ descriptionNo L3$ +
l3$ size0 MiB (0 KiB, 0 B, 0 GiB) +
ldateMarch 2, 2015 +
manufacturerIntel +
market segmentMobile +
max cpu count1 +
max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max operating temperature90 °C +
max pcie lanes2 +
microarchitectureAirmont +
min operating temperature0 °C +
model numberx5-Z8500 +
nameIntel Atom x5-Z8500 +
part numberFJ8066401715814 + and FJ8066401715842 +
platformCherry Trail +
process14 nm (0.014 μm, 1.4e-5 mm) +
s-specSR27N + and SR2GN +
sdp2 W (2,000 mW, 0.00268 hp, 0.002 kW) +
seriesZ8000 +
smp max ways1 +
technologyCMOS +
thread count4 +
turbo frequency (1 core)2,240 MHz (2.24 GHz, 2,240,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +