Semiconductor & Computer Engineering
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Difference between revisions of "Template:integrated memory controller"
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{{#if:{{{type|}}}|{{!-}}|<div></div>}} | {{#if:{{{type|}}}|{{!-}}|<div></div>}} | ||
| − | {{#if:{{{type|}}}|{{!}} '''Type''' {{!}}{{!}} {{{type}}}{{#if:{{{type 1|}}}|, {{{type 1}}}|}}{{#if:{{{type 2|}}}|, {{{type 2}}}|}}{{#if:{{{type 3|}}}|, {{{type 3}}}|}}{{#if:{{{type 4|}}}|, {{{type 4}}}|}}{{#if:{{{type 5|}}}|, {{{type 5}}}|}}|}} | + | {{#if:{{{type|}}}|{{!}} style="min-width: 125px;" {{!}} '''Type''' {{!}}{{!}} {{{type}}}{{#if:{{{type 1|}}}|, {{{type 1}}}|}}<!-- |
| + | -->{{#if:{{{type 2|}}}|, {{{type 2}}}|}}<!-- | ||
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| + | -->{{#if:{{{type 10|}}}|, {{{type 10}}}|}} |}} | ||
{{#if:{{{controllers|}}}|{{!-}}|<div></div>}} | {{#if:{{{controllers|}}}|{{!-}}|<div></div>}} | ||
{{#if:{{{controllers|}}}|{{!}} '''Controllers''' {{!}}{{!}} {{{controllers}}}|}} | {{#if:{{{controllers|}}}|{{!}} '''Controllers''' {{!}}{{!}} {{{controllers}}}|}} | ||
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{{#if:{{{bandwidth qchan|}}}|{{!-}}|<div></div>}} | {{#if:{{{bandwidth qchan|}}}|{{!-}}|<div></div>}} | ||
{{#if:{{{bandwidth qchan|}}}|{{!}} '''Bandwidth (quad)''' {{!}}{{!}} {{{bandwidth qchan}}}|}} | {{#if:{{{bandwidth qchan|}}}|{{!}} '''Bandwidth (quad)''' {{!}}{{!}} {{{bandwidth qchan}}}|}} | ||
| + | {{#if:{{{bandwidth ochan|}}}|{{!-}}|<div></div>}} | ||
| + | {{#if:{{{bandwidth ochan|}}}|{{!}} '''Bandwidth (octa)''' {{!}}{{!}} {{{bandwidth ochan}}}|}} | ||
{{#if:{{{max memory|}}}|{{!-}}|<div></div>}} | {{#if:{{{max memory|}}}|{{!-}}|<div></div>}} | ||
{{#if:{{{max memory|}}}|{{!}} '''Max memory''' {{!}}{{!}} {{{max memory}}}|}} | {{#if:{{{max memory|}}}|{{!}} '''Max memory''' {{!}}{{!}} {{{max memory}}}|}} | ||
| + | {{#if:{{{pae|}}}|{{!-}}|<div></div>}} | ||
| + | {{#if:{{{pae|}}}|{{!}} '''Physical Address Extensions''' {{!}}{{!}} {{{pae}}}|}} | ||
|}<noinclude>{{documentation}} | |}<noinclude>{{documentation}} | ||
</noinclude> | </noinclude> | ||
Latest revision as of 13:10, 3 November 2016
| Integrated Memory Controller |
Code[edit]
== Memory controller ==
{{integrated memory controller
| type =
| type 2 =
| type N =
| controllers =
| channels =
| ecc support =
| max bandwidth =
| bandwidth schan =
| bandwidth dchan =
| bandwidth tchan =
| bandwidth qchan =
| max memory =
| pae =
}}