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{{annapurna title|AWS Graviton4}}
 
{{annapurna title|AWS Graviton4}}
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{{chip}}
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{{chip
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'''AWS Graviton4''' ('''Alpine ALC14C00''') is a [[hexanonaconta-core]] [[ARMv9]] multiprocessor designed by [[Amazon]] ([[Annapurna Labs]]) for Amazon's own infrastructure. Graviton4 is a [[5 nm]](?) 7-chiplet design SoC based on the Arm [[CMN-700 mesh interconnect]] and [[Neoverse V2]] core microarchitecture. This chip supports dodeca-channel DDR5-5600 ECC memory.
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|name=AWS Graviton4
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|image=graviton4.png
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|caption=Graviton4 Package Front
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|designer=Annapurna Labs
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|manufacturer=TSMC
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|model number=Graviton4
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|part number=ALC14C00
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|market=Server
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|first announced=November 28, 2023
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|first launched=November 28, 2023
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|family=Graviton
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|isa=ARMv9.0-A
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|isa family=ARM
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|microarch=Neoverse V2
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|technology=CMOS
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|mcp=Yes
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|die count=7
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|word size=64 bit
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|core count=96
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|thread count=96
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|max cpus=2
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|smp interconnect=CCIX
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|smp interconnect links=3
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|predecessor=Graviton3
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|predecessor link=annapurna_labs/graviton/graviton3
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}}
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'''AWS Graviton4''' ('''Alpine ALC14C00''') is a [[hexanonaconta-core]] [[ARMv9]] multiprocessor designed by [[Amazon]] ([[Annapurna Labs]]) for Amazon's own infrastructure. Graviton4 is a [[5 nm]](?) 7-chiplet design SoC based on the Arm [[CMN-700 mesh interconnect]] and [[Neoverse V2]] core microarchitecture. This chip supports dodeca-channel DDR5-5600 ECC memory along with 96 lanes of PCIe 5.0.
  
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This 4th-generation server processor was first announced during Amazon's AWS re:Invent 2023 by Adam Selipsky in his keynote. The general rollout for the Graviton4 chip in the AWS data center took place in early 2024. These processors are offered as part of Amazon's EC2 instances.
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== Overview ==
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This 4th-generation server processor was first announced during Amazon's AWS re:Invent [[2023]] by Adam Selipsky in his keynote. The general rollout for the Graviton4 chip in the AWS data center occurred in early 2024. These processors are offered as part of Amazon's EC2 instances.
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Graviton4 features a 7-chiplet design similar to its predecessor, {{\\|Graviton3}}. This chip features 96 cores, 50% more than the prior generation. The core implementation was updated to Arm's {{armh|Neoverse V2}} microarchitecture with 2x256b [[Scalable Vector Extension|SVE]] support, also bringing support up to [[Armv9.0]] ISA for the first time. The chip supports up to 12 channels for DDR5 ECC DIMMs with data rates of up to 5600 MT/s. The Graviton4 tripled the number of PCIe lanes to 96 lanes of PCIe 5.0.
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[[File:graviton4 layout.png|thumb|left]]
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The Graviton4 is the first chip from the Graviton family to feature multiprocessing support. The chip introduced dual-socket support with full coherency for up to 192 vCPUs and DDR5 channels on a single server. The Graviton4 also expanded encryption support to the new multi-socket coherency links as well as to the Nitro cards interfaces. The full platform can be configured to run in a number of modes that can potentially offer additional power saving: two non-coherent virtual systems, one coherent virtual system, two metal systems, or one metal system.
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{{clear|left}}[[File:graviton4 sockets.png|thumb|right]] [[File:graviton4 server.png|thumb|right]] [[File:graviton4 held.png|thumb|right]]
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=== Packaging ===
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The Graviton4 features a 7-chiplet architecture similar in design to the Graviton3. The compute SoC die sits in the middle with 4 DDR memory controller dies and 2 PCIe controller dies. Each DDR memory controller features support for 3 memory channels - two dies to the east and two dies to the west for a total of 6 memory channels on each side. There are two PCIe controller dies - one to the north and one to the south of the chip. The four DDR memory controller dies are interconnected with the SoC via embedded silicon bridges in the package.Unlike the {{\\|Graviton3}}, the two PCIe controller dies are not abutting the compute SoC die and are no longer controller via an embedded bridge in the package.
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== Cache ==
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{{main|arm_holdings/microarchitectures/neoverse v2#Memory_Hierarchy|l1=Neoverse V2 § Cache}}
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{{cache size
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|l1 cache=12 MiB
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|l1i cache=6 MiB
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|l1i break=96x64 KiB
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|l1d cache=6 MiB
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|l1d break=96x64 KiB
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|l2 cache=192 MiB
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|l2 break=96x2 MiB
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}}
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== Memory controller ==
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{{memory controller
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|type=DDR5-5600
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|ecc=Yes
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|controllers=4
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|channels=12
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|max bandwidth=537.6 GB/s
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|bandwidth schan=44.8 GB/s
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|bandwidth dchan=89.6 GB/s
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|bandwidth qchan=179.2 GB/s
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|bandwidth ochan=358.4 GB/s
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|bandwidth 10chan=448.0 GB/s
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|bandwidth 12chan=537.6 GB/s
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}}
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== Expansions ==
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{{expansions
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| pcie revision      = 5.0
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| pcie lanes        = 96
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| pcie config        = x16
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| pcie config 2      = x8
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| pcie config 3      = x4
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}}

Latest revision as of 00:50, 12 December 2023

Edit Values
AWS Graviton4
graviton4.png
Graviton4 Package Front
General Info
DesignerAnnapurna Labs
ManufacturerTSMC
Model NumberGraviton4
Part NumberALC14C00
MarketServer
IntroductionNovember 28, 2023 (announced)
November 28, 2023 (launched)
General Specs
FamilyGraviton
Microarchitecture
ISAARMv9.0-A (ARM)
MicroarchitectureNeoverse V2
TechnologyCMOS
MCPYes (7 dies)
Word Size64 bit
Cores96
Threads96
Multiprocessing
Max SMP2-Way (Multiprocessor)
InterconnectCCIX
Interconnect Links3
Succession

AWS Graviton4 (Alpine ALC14C00) is a hexanonaconta-core ARMv9 multiprocessor designed by Amazon (Annapurna Labs) for Amazon's own infrastructure. Graviton4 is a 5 nm(?) 7-chiplet design SoC based on the Arm CMN-700 mesh interconnect and Neoverse V2 core microarchitecture. This chip supports dodeca-channel DDR5-5600 ECC memory along with 96 lanes of PCIe 5.0.

Overview[edit]

This 4th-generation server processor was first announced during Amazon's AWS re:Invent 2023 by Adam Selipsky in his keynote. The general rollout for the Graviton4 chip in the AWS data center occurred in early 2024. These processors are offered as part of Amazon's EC2 instances.

Graviton4 features a 7-chiplet design similar to its predecessor, Graviton3. This chip features 96 cores, 50% more than the prior generation. The core implementation was updated to Arm's Neoverse V2 microarchitecture with 2x256b SVE support, also bringing support up to Armv9.0 ISA for the first time. The chip supports up to 12 channels for DDR5 ECC DIMMs with data rates of up to 5600 MT/s. The Graviton4 tripled the number of PCIe lanes to 96 lanes of PCIe 5.0.

graviton4 layout.png

The Graviton4 is the first chip from the Graviton family to feature multiprocessing support. The chip introduced dual-socket support with full coherency for up to 192 vCPUs and DDR5 channels on a single server. The Graviton4 also expanded encryption support to the new multi-socket coherency links as well as to the Nitro cards interfaces. The full platform can be configured to run in a number of modes that can potentially offer additional power saving: two non-coherent virtual systems, one coherent virtual system, two metal systems, or one metal system.

graviton4 sockets.png
graviton4 server.png
graviton4 held.png

Packaging[edit]

The Graviton4 features a 7-chiplet architecture similar in design to the Graviton3. The compute SoC die sits in the middle with 4 DDR memory controller dies and 2 PCIe controller dies. Each DDR memory controller features support for 3 memory channels - two dies to the east and two dies to the west for a total of 6 memory channels on each side. There are two PCIe controller dies - one to the north and one to the south of the chip. The four DDR memory controller dies are interconnected with the SoC via embedded silicon bridges in the package.Unlike the Graviton3, the two PCIe controller dies are not abutting the compute SoC die and are no longer controller via an embedded bridge in the package.

Cache[edit]

Main article: Neoverse V2 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$12 MiB
12,288 KiB
12,582,912 B
L1I$6 MiB
6,144 KiB
6,291,456 B
96x64 KiB  
L1D$6 MiB
6,144 KiB
6,291,456 B
96x64 KiB  
L2$192 MiB
196,608 KiB
201,326,592 B
0.188 GiB
  96x2 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR5-5600
Supports ECCYes
Controllers4
Channels12
Max Bandwidth537.6 GB/s
500.679 GiB/s
512,695.313 MiB/s
537,600 MB/s
0.489 TiB/s
0.538 TB/s
Bandwidth
Single 44.8 GB/s
Double 89.6 GB/s
Quad 179.2 GB/s
Octa 358.4 GB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision5.0
Max Lanes96
Configsx16, x8, x4
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