Difference between revisions of "intel/80486"

Latest revision as of 07:27, 29 October 2022

Intel 80486

Intel A80486DX-25
Developer	Intel
Manufacturer	Intel
Type	Microprocessors
Introduction	April 10, 1989 (announced) June, 1989 (launch)
Production	1988-2007
Architecture	x86
ISA	IA-32
µarch	80486
Word size	32 bit 4 octets 8 nibbles
Process	1 µm 1,000 nm 0.001 mm , 800 nm 0.8 μm 8.0e-4 mm , 600 nm 0.6 μm 6.0e-4 mm
Technology	CMOS
Clock	16 MHz-100 MHz
Package	PGA-168, PQFP-196, SQFP-208
Succession
←	→
80386	Pentium

The 80486, also i486 and 486, (pronounced eighty-four-eighty-six) was a family of 32-bit 4th-generation x86 microprocessors introduced by Intel in 1989 as a successor to the 80386. 486 introduced a number of enhancements to 386 including a new level 1 cache, better IPC performance, and an integrated FPU. The 486 became the first x86 chip family to exceed one million transistors.

Architecture[edit]

Main article: 80486 Microarchitectures

Like its predecessor, the 80486 maintains full backwards object code comparability with the all previous x86 processors (80386, 80286, 80186, etc...). To improve performance Intel introduced a new layer of cache on-die (previously various external extensions existed). The 8 KB, 4-way set associative, write-back policy, cache was unified for both the data and instructions. This provided much needed faster access to recently used data and instructions. Various enhancements were also made to the bus interface including faster communication that required single clock cycle instead of multiple.

Whereas before a separately packaged math coprocessor was used (i.e. 80387, 80287, etc..), the 80486 moved the unit on-die eliminating the external communication delays altogether. Furthermore more aggressive math algorithms were used to implement the new FPU yielding faster floating point calculations.

The pipeline itself received some attention as well. Simple ALU register, register and register, immediate cached operations could now complete in a single cycle; this previously required at least 2 cycles.

Members[edit]

i486DX[edit]

i486DX Processors
Model	Launched	Process	Freq	Max Mem
i486DX-20	June 1989	1,000 nm 1 μm 0.001 mm 800 nm 0.8 μm 8.0e-4 mm	20 MHz 0.02 GHz 20,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486DX-25	June 1989	1,000 nm 1 μm 0.001 mm 800 nm 0.8 μm 8.0e-4 mm	25 MHz 0.025 GHz 25,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486DX-33	7 May 1990	1,000 nm 1 μm 0.001 mm 800 nm 0.8 μm 8.0e-4 mm	33 MHz 0.033 GHz 33,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486DX-50	24 June 1991	1,000 nm 1 μm 0.001 mm 800 nm 0.8 μm 8.0e-4 mm	50 MHz 0.05 GHz 50,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486DX2-40	3 March 1992	1,000 nm 1 μm 0.001 mm 800 nm 0.8 μm 8.0e-4 mm	40 MHz 0.04 GHz 40,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486DX2-50	3 March 1992	1,000 nm 1 μm 0.001 mm 800 nm 0.8 μm 8.0e-4 mm	50 MHz 0.05 GHz 50,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486DX2-66	3 March 1992	1,000 nm 1 μm 0.001 mm 800 nm 0.8 μm 8.0e-4 mm	66 MHz 0.066 GHz 66,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486DX4-100	7 March 1994	600 nm 0.6 μm 6.0e-4 mm	100 MHz 0.1 GHz 100,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486DX4-75	7 March 1994	600 nm 0.6 μm 6.0e-4 mm	75 MHz 0.075 GHz 75,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
Count: 9

i486SX[edit]

i486SX Processors
Model	Launched	Process	Freq	Max Mem
i486SX-16	22 April 1991	1,000 nm 1 μm 0.001 mm 800 nm 0.8 μm 8.0e-4 mm	16 MHz 0.016 GHz 16,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486SX-20	16 September 1991	1,000 nm 1 μm 0.001 mm 800 nm 0.8 μm 8.0e-4 mm	20 MHz 0.02 GHz 20,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486SX-25	16 September 1991	1,000 nm 1 μm 0.001 mm 800 nm 0.8 μm 8.0e-4 mm	25 MHz 0.025 GHz 25,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486SX-33	21 September 1992	1,000 nm 1 μm 0.001 mm 800 nm 0.8 μm 8.0e-4 mm	33 MHz 0.033 GHz 33,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486SX2-50		800 nm 0.8 μm 8.0e-4 mm	50 MHz 0.05 GHz 50,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486SX2-66		800 nm 0.8 μm 8.0e-4 mm	66 MHz 0.066 GHz 66,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
Count: 6

i486SL[edit]

i486SL Processors
Model	Launched	Process	Freq	Max Mem
i486SL-20	9 November 1992	800 nm 0.8 μm 8.0e-4 mm	20 MHz 0.02 GHz 20,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486SL-25	9 November 1992	800 nm 0.8 μm 8.0e-4 mm	25 MHz 0.025 GHz 25,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
i486SL-33	9 November 1992	800 nm 0.8 μm 8.0e-4 mm	33 MHz 0.033 GHz 33,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
Count: 3

i486GX[edit]

i486GX Processors
Model	Launched	Process	Freq	Max Mem
i486GX-33		800 nm 0.8 μm 8.0e-4 mm	33 MHz 0.033 GHz 33,000 kHz	4,096 MiB 4,194,304 KiB 4,294,967,296 B 4 GiB 0.00391 TiB
Count: 1

Clones[edit]

Am486

This list is incomplete; you can help by expanding it.

Documents[edit]

Datasheet[edit]

Manual[edit]

@@ Line 1: / Line 1: @@
 {{intel title|80486}}
 {{ic family
-| title             = Cum sock ass
+| title             = Intel 80486
 | image             = Intel i486 DX 25MHz SX328.jpg
 | caption           = Intel A80486DX-25
@@ Line 8: / Line 8: @@
 | type              = Microprocessors
 | first announced   = April 10, 1989
-| first launched    = June, balls sack
+| first launched    = June, 1989
 | production start  = 1988
 | production end    = 2007
@@ Line 34: / Line 34: @@
 == Architecture ==
 {{main|intel/microarchitectures/80486|l1=80486 Microarchitectures}}
-Like {{\\|80386|its predecessor}}, the 80486 maintains full backwards [[object code]] comparability with the all previous [[x86]] processors ({{\\|80386}}, {{\\|80286}},  {{\\|80186}}, etc...). To improve performance Intel introduced a new layer of ball cum (previously various external extensions existed). The 8 KB, 4-way set associative, write-back policy, cache was unified for both the data and instructions. This provided much needed faster access to recently used data and instructions. Various enhancements were also made to the bus interface including faster communication that required single clock cycle instead of multiple.
+Like {{\\|80386|its predecessor}}, the 80486 maintains full backwards [[object code]] comparability with the all previous [[x86]] processors ({{\\|80386}}, {{\\|80286}},  {{\\|80186}}, etc...). To improve performance Intel introduced a new layer of cache on-die (previously various external extensions existed). The 8 KB, 4-way set associative, write-back policy, cache was unified for both the data and instructions. This provided much needed faster access to recently used data and instructions. Various enhancements were also made to the bus interface including faster communication that required single clock cycle instead of multiple.
 Whereas before a separately packaged [[FPU|math]] [[coprocessor]] was used (i.e. {{\\|80387}}, {{\\|80287}}, etc..), the 80486 moved the unit on-die eliminating the external communication delays altogether. Furthermore more aggressive math algorithms were used to implement the new [[FPU]] yielding faster floating point calculations.
@@ Line 48: / Line 48: @@
             created and tagged accordingly.
-            Missing a ball? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
+            Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 -->
 <table class="wikitable sortable">
-<tr><th colspan="16" style="background:#D6D6FF;">i487DX Processors</th></tr>
+<tr><th colspan="16" style="background:#D6D6FF;">i486DX Processors</th></tr>
 <tr><th>Model</th><th>Launched</th><th>Process</th><th>Freq</th><th>Max Mem</th></tr>
 {{#ask: [[Category:microprocessor models by intel]][[instance of::microprocessor]][[microprocessor family::80486]][[core name::~486DX*]]
   |?full page name
   |?model number
-  |?ball sack
+  |?first launched
   |?process
   |?base frequency#MHz

designer	Intel +
first announced	April 10, 1989 +
full page name	intel/80486 +
instance of	microprocessor family +
instruction set architecture	IA-32 +
main designer	Intel +
manufacturer	Intel +
microarchitecture	80486 +
name	Cum sock ass +
package	PGA-168 +, PQFP-196 + and SQFP-208 +
process	1,000 nm (1 μm, 0.001 mm) +, 800 nm (0.8 μm, 8.0e-4 mm) + and 600 nm (0.6 μm, 6.0e-4 mm) +
word size	32 bit (4 octets, 8 nibbles) +

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