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=== Key changes from {{\\|Zen 3}} ===
 
=== Key changes from {{\\|Zen 3}} ===
 
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* raised core/thread count from 64/128 to at least 96/192 (vastly due to 5nm process allowing more space, therefore more cores).
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* Raised maximum core/thread count from 64/128 to at least 96/192 (vastly due to 5nm process allowing more space, therefore more cores).
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* improved cache load, write and prefetch from/to register (less latency).
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* Improved cache load, write and prefetch from/to register (less latency).
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* improved iGPUs for APU variants; navi integrated gpu with up to 3.4 TFLOPs FP32 (clock frequency unknown, at least 2 GHz).
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* Utilizes new AM5 socket and is expected to support DDR5 and confirmed PCI-E 5.
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* utilizes new AM5 socket and is expected to support DDR5 and possibly PCIe 5.
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* More transistors (depending on AM5 socket as well and not just the CPU it self).
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* more transistors (depending on AM5 socket as well and not just the CPU it self).
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*Double the L2 cache when compared to Zen 3
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*double the L2 cache when compared to Zen 3
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*Capable of higher all-core clockspeeds (shown 5GHz+)
  
 
== Bibliography ==
 
== Bibliography ==

Revision as of 18:43, 8 January 2022

Edit Values
Zen 4 µarch
General Info
Arch TypeCPU
DesignerAMD
ManufacturerTSMC
Process5 nm
Succession

Zen 4 is a planned microarchitecture being developed by AMD as a successor to Zen 3.

History

Zen 4 on the roadmap.

Zen 4 was first mentioned by Forrest Norrod during AMD's EPYC One Year Anniversary webinar. During the next horizon event which was held on November 6, 2018, AMD stated that Zen 4 was at the design completion phase.

Process Technology

AMD claims that Zen4 is going to be produced on a 5nm node by TSMC.

Codenames

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Core C/T Target
Genoa Up to 96/192 High-end server multiprocessors
Warhol Up to 20/40 Mainstream to high-end desktops & enthusiasts market processors
Rembrandt Up to 8/16 Mainstream desktop & mobile processors with GPU

Cores using variant Zen 4 uarch:

Core C/T Target
Bergamo Up to 128/128? Cloud multiprocessing (smaller, almost half-size Zen 4c [referred to as “Zen 4D” in leaks] core likely sacrificing AVX-512, L3 and possibly SMT)

Architecture

Little is currently known about the architectural improvements that are being done to Zen 4.

Key changes from Zen 3

New text document.svg This section is empty; you can help add the missing info by editing this page.
  • Raised maximum core/thread count from 64/128 to at least 96/192 (vastly due to 5nm process allowing more space, therefore more cores).
  • Improved cache load, write and prefetch from/to register (less latency).
  • Utilizes new AM5 socket and is expected to support DDR5 and confirmed PCI-E 5.
  • More transistors (depending on AM5 socket as well and not just the CPU it self).
  • Double the L2 cache when compared to Zen 3
  • Capable of higher all-core clockspeeds (shown 5GHz+)

Bibliography

Designers

  • Mike Clark(?), chief architect

Bibliography

See Also

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Facts about "Zen 4 - Microarchitectures - AMD"
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codenameZen 4 +
designerAMD +
full page nameamd/microarchitectures/zen 4 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameZen 4 +
process5 nm (0.005 μm, 5.0e-6 mm) +