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{{amd title|AMD-K6-200ALR}} | {{amd title|AMD-K6-200ALR}} | ||
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| name = AMD-K6-200ALR | | name = AMD-K6-200ALR | ||
| no image = Yes | | no image = Yes | ||
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| thread count = 1 | | thread count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| max memory addr = | | max memory addr = | ||
| − | + | ||
| power = 20 W | | power = 20 W | ||
| v core = 2.9 V | | v core = 2.9 V | ||
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}} | }} | ||
'''AMD-K6-200ALR''' was a {{arch|32}} [[x86]] microprocessor designed by [[AMD]] and introduced in early [[1997]]. This chip, which was based on AMD's new {{amd|microarchitectures/k6|K6 microarchitecture}}, operated at 200 MHz and dissipated a maximum of 20 W. | '''AMD-K6-200ALR''' was a {{arch|32}} [[x86]] microprocessor designed by [[AMD]] and introduced in early [[1997]]. This chip, which was based on AMD's new {{amd|microarchitectures/k6|K6 microarchitecture}}, operated at 200 MHz and dissipated a maximum of 20 W. | ||
| + | |||
| + | == Cache == | ||
| + | {{main|amd/microarchitectures/k6#Memory_Hierarchy|l1=K6 § Cache}} | ||
| + | [[L2$]] can be 256 KiB to 1 MiB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip. | ||
| + | {{cache info | ||
| + | |l1i cache=32 KiB | ||
| + | |l1i break=1x32 KiB | ||
| + | |l1i desc=2-way set associative | ||
| + | |l1i extra= | ||
| + | |l1d cache=32 KiB | ||
| + | |l1d break=1x32 KiB | ||
| + | |l1d desc=2-way set associative | ||
| + | |l1d extra= | ||
| + | |l2 cache= | ||
| + | |l2 break= | ||
| + | |l2 desc= | ||
| + | |l2 extra= | ||
| + | |l3 cache= | ||
| + | |l3 break= | ||
| + | |l3 desc= | ||
| + | |l3 extra= | ||
| + | }} | ||
| + | |||
| + | == Graphics == | ||
| + | This SoC has no integrated graphics processing unit. | ||
| + | |||
| + | == Features == | ||
| + | {{x86 features | ||
| + | | mmx = true | ||
| + | }} | ||
| + | * Auto-power down state | ||
| + | * Stop clock state | ||
| + | |||
| + | == Documents == | ||
| + | === DataSheet === | ||
| + | * [[:File:AMD-K6 Processor DataSheet (June, 1997).pdf|AMD-K6 MMX Enhanced Processor Multimedia Technology]]; Publication #20695 Revision E/0; June 1997 | ||
Latest revision as of 00:23, 9 November 2020
| Edit Values | |
| AMD-K6-200ALR | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | AMD-K6-200ALR |
| Part Number | AMD-K6-200ALR |
| Market | Desktop |
| Introduction | May, 1997 (announced) May, 1997 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | K6 |
| Series | Desktop K6 |
| Locked | No |
| Frequency | 199.99 MHz |
| Bus type | FSB |
| Bus speed | 66.66 MHz |
| Bus rate | 66.66 MT/s |
| Clock multiplier | 3 |
| CPUID | 560 |
| Microarchitecture | |
| Microarchitecture | K6 |
| Core Name | 6k86 |
| Core Family | 5 |
| Core Model | 6 |
| Process | 350 nm |
| Transistors | 8,800,000 |
| Technology | CMOS |
| Die | 162 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 20 W |
| Vcore | 2.9 V ± 5% |
| VI/O | 3.3 V ± 5% |
| Tcase | 0 °C – 70 °C |
| Tstorage | -65 °C – 150 °C |
AMD-K6-200ALR was a 32-bit x86 microprocessor designed by AMD and introduced in early 1997. This chip, which was based on AMD's new K6 microarchitecture, operated at 200 MHz and dissipated a maximum of 20 W.
Contents
Cache[edit]
- Main article: K6 § Cache
L2$ can be 256 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
| L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
|
|
|
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- Auto-power down state
- Stop clock state
Documents[edit]
DataSheet[edit]
- AMD-K6 MMX Enhanced Processor Multimedia Technology; Publication #20695 Revision E/0; June 1997
Facts about "AMD-K6-200ALR - AMD"
| l1d$ description | 2-way set associative + |
| l1i$ description | 2-way set associative + |