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Difference between revisions of "intel/microarchitectures/rocket lake"
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{{intel title|Rocket Lake|arch}} | {{intel title|Rocket Lake|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
| − | |atype= | + | |atype=APU |
|name=Rocket Lake | |name=Rocket Lake | ||
|designer=Intel | |designer=Intel | ||
Revision as of 09:08, 21 October 2020
| Edit Values | |
| Rocket Lake µarch | |
| General Info | |
| Arch Type | APU |
| Designer | Intel |
| Manufacturer | Intel |
| Process | 14 nm |
| Core Configs | 4 |
| Pipeline | |
| Type | Superscalar, Superpipeline |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 14-19 |
| Decode | 5-way |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX |
| Cache | |
| L1I Cache | 48 KiB/core 8-way set associative |
| L1D Cache | 32 KiB/core 8-way set associative |
| L2 Cache | 512 KiB/core 4-way set associative |
| L3 Cache | 2 MiB/core Up to 16-way set associative |
| L4 Cache | 128 MiB/package on Iris Pro GPUs only |
| Succession | |
| Contemporary | |
| Tiger Lake | |
Rocket Lake (RKL) is a planned microarchitecture designed by Intel as a successor to Comet Lake for desktops and high-performance mobile devices.
Contents
Codenames
| Core | Description | Graphics | Target |
|---|---|---|---|
| Rocket Lake S | Mainstream performance | GT2 | Desktop performance to value, AiOs, and minis |
| Rocket Lake U | Ultra-low power | GT2 | Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
Brands
Intel is expected to release Rocket Lake under 3 main brand families:
| Logo | Family | General Description | Differentiating Features | |||||
|---|---|---|---|---|---|---|---|---|
| Cores | HT | AVX | AVX2 | TBT | ECC | |||
 |
Core i3 | Low-end Performance | ||||||
 |
Core i5 | Mid-range Performance | ||||||
 |
Core i7 | High-end Performance | ||||||
Release Dates
Rocket Lake is expected to be released in Q1 2021.
Compatibility
 |
This section is empty; you can help add the missing info by editing this page. |
Compiler support
| Compiler | Arch-Specific | Arch-Favorable |
|---|---|---|
| ICC | -march=skylake |
-mtune=skylake
|
| GCC | -march=skylake |
-mtune=skylake
|
| LLVM | -march=skylake |
-mtune=skylake
|
| Visual Studio | /arch:AVX2 |
/tune:skylake
|
CPUID
| |
This section is empty; you can help add the missing info by editing this page. |
Architecture
Key changes from Comet Lake
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
- Core
- Display
- DisplayPort 1.4a (from DisplayPort 1.2)
- HDMI 2.0b (from HDMI 1.4b)
- I/O
- PCIe 4.0 (from 3.0)
- Memory
- Faster memory for mainstream desktops (i.e., Rocket Lake S) DDR4-3200 (from DDR4-2993)
- Chipset
- 400 Series chipset → 500 Series chipset
- 2.5G Ethernet (Foxville) support
- Integrated WiFi 6 AX201 (GiG+) support via CNVi
- 400 Series chipset → 500 Series chipset
- Packaging
- Die thinning on top-end SKUs for better heat removal
See also
Facts about "Rocket Lake - Microarchitectures - Intel"
| codename | Rocket Lake + |
| core count | 4 + |
| designer | Intel + |
| full page name | intel/microarchitectures/rocket lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| name | Rocket Lake + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |