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Difference between revisions of "intel/microarchitectures/tiger lake"
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Revision as of 16:54, 5 August 2020
| Edit Values | |
| Tiger Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | September 2, 2020 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
| Contemporary | |
| Sapphire Rapids | |
Tiger Lake (TGL) is Intel's successor to Ice Lake, a 10nm microarchitecture for mainstream workstations, desktops, and mobile devices.
Process Technology
- Main article: Cannon Lake § Process Technology
Tiger Lake will be manufactured on Intel's third generation enhanced 10nm++ process.
History
Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2020.
Architecture
Not much is known about Tiger Lake's architecture.
Key changes from Ice Lake
- Core
- Sunny Cove ➡ Willow Cove
- Up to 50% larger Level 3 cache - 3MB per core from 2MB per core
- 2,25x larger Level 2 cache - 1,25MB per core from 512KB per core
- GPU
- Display
- HDMI 2.1 (from HDMI 2.0b)
- I/O
- PCIe 4.0 (from 3.0)
- Hardware Telemetry
- Intel Platform Monitoring Technology provides access to hardware performance, sampling and tracing data.
Facts about "Tiger Lake - Microarchitectures - Intel"
| codename | Tiger Lake + |
| designer | Intel + |
| first launched | September 2, 2020 + |
| full page name | intel/microarchitectures/tiger lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tiger Lake + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |