Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "Template:x86 isa main"
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* {{x86|Addressing Modes}} | * {{x86|Addressing Modes}} | ||
* {{x86|Registers}} | * {{x86|Registers}} | ||
| + | * {{x86|Model-Specific Register}} | ||
* {{x86|Assembly}} | * {{x86|Assembly}} | ||
| − | |||
* {{x86|Interrupts}} | * {{x86|Interrupts}} | ||
* {{x86|Micro-Ops}} | * {{x86|Micro-Ops}} | ||
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* {{x86|Calling Convention}} | * {{x86|Calling Convention}} | ||
* {{x86|Microarchitectures}} | * {{x86|Microarchitectures}} | ||
| + | * {{x86|CPUID}} | ||
| + | <div class="header">CPUIDs</div> | ||
| + | * {{amd|CPUID|AMD's CPUIDs}} | ||
| + | * {{intel|CPUID|Intel's CPUIDs}} | ||
<div class="header">Modes</div> | <div class="header">Modes</div> | ||
* {{x86|Real Mode|Real}} | * {{x86|Real Mode|Real}} | ||
| Line 25: | Line 29: | ||
<div class="header">Extensions<small style="float: right;">({{x86|Extensions|all}})</small></div> | <div class="header">Extensions<small style="float: right;">({{x86|Extensions|all}})</small></div> | ||
<div class="wiki-ul-col3"> | <div class="wiki-ul-col3"> | ||
| − | * {{x86| | + | * {{x86|3DNow!}} |
| + | * {{x86|ABM}} | ||
| + | * {{x86|ADX}} | ||
| + | * {{x86|AES}} | ||
| + | * {{x86|AMX}} | ||
| + | * {{x86|AVX}} | ||
| + | * {{x86|AVX2}} | ||
| + | * {{x86|AVX-512}} | ||
| + | * {{x86|BMI1}} | ||
| + | * {{x86|BMI2}} | ||
| + | * {{x86|CLMUL}} | ||
| + | * {{x86|E3DNow!}} | ||
| + | * {{x86|EMMX}} | ||
| + | * {{x86|F16C}} | ||
| + | * {{x86|FMA3}} | ||
| + | * {{x86|FMA4}} | ||
* {{x86|FPU}} | * {{x86|FPU}} | ||
| + | * {{x86|MKTME}} | ||
* {{x86|MMX}} | * {{x86|MMX}} | ||
| − | * {{x86| | + | * {{x86|MPX}} |
| + | * {{x86|persistent memory extensions|PMEM}} | ||
| + | * {{x86|PREFETCH}} | ||
| + | * {{x86|RdRAND}} | ||
| + | * {{x86|SEV}} | ||
| + | * {{x86|SGX}} | ||
| + | * {{x86|SHA}} | ||
| + | * {{x86|SME}} | ||
| + | * {{x86|SMM}} | ||
| + | * {{x86|SMX}} | ||
* {{x86|SSE}} | * {{x86|SSE}} | ||
| − | |||
| − | |||
* {{x86|SSE2}} | * {{x86|SSE2}} | ||
* {{x86|SSE3}} | * {{x86|SSE3}} | ||
| − | |||
* {{x86|SSE4.1}} | * {{x86|SSE4.1}} | ||
* {{x86|SSE4.2}} | * {{x86|SSE4.2}} | ||
* {{x86|SSE4a}} | * {{x86|SSE4a}} | ||
| − | |||
* {{x86|SSE5}} | * {{x86|SSE5}} | ||
| − | * {{x86| | + | * {{x86|SSSE3}} |
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
* {{x86|TBM}} | * {{x86|TBM}} | ||
| − | * {{x86| | + | * {{x86|TME}} |
| − | * {{x86| | + | * {{x86|TSME}} |
* {{x86|TSX}} | * {{x86|TSX}} | ||
| − | * {{x86| | + | * {{x86|XOP}} |
| − | + | </div>{{Navbar|Template:x86 isa main|text=|mini=1|style=float:right;}} | |
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | </div> | ||
| − | {{Navbar|Template:x86 isa main|text=|mini=1|style=float:right;}} | ||
</div> | </div> | ||
Latest revision as of 22:37, 28 June 2020
x86
Instruction Set Architecture
Instruction Set Architecture
General
Variants
Topics
- Instructions
- Addressing Modes
- Registers
- Model-Specific Register
- Assembly
- Interrupts
- Micro-Ops
- Timer
- Calling Convention
- Microarchitectures
- CPUID
CPUIDs
Modes
Extensions(all)