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− | <table style="border: solid 1px #a7d7f9; width: 375px; float: right; margin: 0 10px 10px 10px; text-align: left; font-size: 12px;"> | + | <div class="guidebox"> |
− | <tr><td style="text-align: center;" colspan="3">[[x86|<span style="text-decoration: none; color: #555555; text-shadow: 0px 2px 3px #222222; font-size: 60pt; font-weight: bold;">x86</span>]]<br><span style="font-size: 20pt;">Instruction Set Architecture</span></td></tr> | + | <div style="text-align: center;">[[x86|<span style="color: rgba(0,0,0,.53); text-shadow: 0px 2px 3px rgba(0,0,0,.33); font-size: 20pt; font-weight: bold; ">x86</span>]]<br>'''Instruction Set Architecture'''</div> |
− | <tr style="text-align: center;"><td style="border-top: 1px solid #a7d7f9;" colspan="3"></td></tr> | + | <div class="header">General</div> |
− | <tr style="text-align: center;"><td>{{x86|History}}</td><td>{{x86|list of processor families|Families}}</td><td></td></tr>
| + | * {{x86|History}} |
− | <tr style="text-align: center;"><td style="border-top: 1px solid #a7d7f9;" colspan="3">Variants</td></tr> | + | * {{x86|list of processor families|Families}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|x86-16}}</td><td>{{x86|x86-32}}</td><td>{{x86|x86-64}}</td></tr>
| + | <div class="header">Variants</div> |
− | <tr style="text-align: center;"><td style="border-top: 1px solid #a7d7f9;" colspan="3">Topics</td></tr> | + | * {{x86|x86-16}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|Instruction Listing|Instructions}}</td><td>{{x86|Addressing Modes}}</td><td>{{x86|Registers}}</td></tr>
| + | * {{x86|x86-32}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|Assembly}}</td><td>{{x86|CPUID}}</td><td>{{x86|Interrupts}}</td></tr>
| + | * {{x86|x86-64}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|Micro-Ops}}</td><td>{{x86|Timer}}</td><td>{{x86|Calling Convention}}</td></tr>
| + | <div class="header">Topics</div> |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|Microarchitectures}}</td><td></td><td></td></tr>
| + | * {{x86|Instruction Listing|Instructions}} |
− | <tr style="text-align: center;"><td style="border-top: 1px solid #a7d7f9;" colspan="3">Modes</td></tr> | + | * {{x86|Addressing Modes}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|Real Mode|Real}}</td><td>{{x86|Protected Mode|Protected}}</td><td>{{x86|Long Mode|Long}}</td></tr> | + | * {{x86|Registers}} |
− | <tr style="text-align: center;"><td style="border-top: 1px solid #a7d7f9;" colspan="3">{{x86|Extensions}}</td></tr> | + | * {{x86|Model-Specific Register}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|SMM}}</td><td>{{x86|FPU}}</td><td>{{x86|MMX}}</td></tr> | + | * {{x86|Assembly}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|3DNow!}}</td><td>{{x86|SSE}}</td><td>{{x86|E3DNow!}}</td></tr>
| + | * {{x86|Interrupts}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|EMMX}}</td><td>{{x86|SSE2}}</td><td>{{x86|SSE3}}</td></tr>
| + | * {{x86|Micro-Ops}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|SSSE3}}</td><td>{{x86|SSE4.1}}</td><td>{{x86|SSE4.2}}</td></tr>
| + | * {{x86|Timer}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|SSE4a}}</td><td>{{x86|ABM}}</td><td>{{x86|SSE5}}</td></tr>
| + | * {{x86|Calling Convention}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|XOP}}</td><td>{{x86|CLMUL}}</td><td>{{x86|AVX}}</td></tr>
| + | * {{x86|Microarchitectures}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|F16C}}</td><td>{{x86|FMA3}}</td><td>{{x86|FMA4}}</td></tr>
| + | * {{x86|CPUID}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|SMX}}</td><td>{{x86|AES}}</td><td>{{x86|TBM}}</td></tr>
| + | <div class="header">CPUIDs</div> |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|BMI1}}</td><td>{{x86|BMI2}}</td><td>{{x86|TSX}}</td></tr>
| + | * {{amd|CPUID|AMD's CPUIDs}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|AVX2}}</td><td>{{x86|ADX}}</td><td>{{x86|RdRAND}}</td></tr>
| + | * {{intel|CPUID|Intel's CPUIDs}} |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|PREFETCH}}</td><td>{{x86|AVX-512}}</td><td>{{x86|MPX}}</td></tr>
| + | <div class="header">Modes</div> |
− | <tr style="text-align: center; border-top: 1px solid #a7d7f9;"><td>{{x86|SGX}}</td><td>{{x86|SHA}}</td><td></td></tr>
| + | * {{x86|Real Mode|Real}} |
− | <tr><td></td><td></td><td style="text-align: right;">[[Template:x86 isa main|[t]]]</td></tr>
| + | * {{x86|Protected Mode|Protected}} |
− | </table> | + | * {{x86|Long Mode|Long}} |
| + | <div class="header">Extensions<small style="float: right;">({{x86|Extensions|all}})</small></div> |
| + | <div class="wiki-ul-col3"> |
| + | * {{x86|3DNow!}} |
| + | * {{x86|ABM}} |
| + | * {{x86|ADX}} |
| + | * {{x86|AES}} |
| + | * {{x86|AMX}} |
| + | * {{x86|AVX}} |
| + | * {{x86|AVX2}} |
| + | * {{x86|AVX-512}} |
| + | * {{x86|BMI1}} |
| + | * {{x86|BMI2}} |
| + | * {{x86|CLMUL}} |
| + | * {{x86|E3DNow!}} |
| + | * {{x86|EMMX}} |
| + | * {{x86|F16C}} |
| + | * {{x86|FMA3}} |
| + | * {{x86|FMA4}} |
| + | * {{x86|FPU}} |
| + | * {{x86|MKTME}} |
| + | * {{x86|MMX}} |
| + | * {{x86|MPX}} |
| + | * {{x86|persistent memory extensions|PMEM}} |
| + | * {{x86|PREFETCH}} |
| + | * {{x86|RdRAND}} |
| + | * {{x86|SEV}} |
| + | * {{x86|SGX}} |
| + | * {{x86|SHA}} |
| + | * {{x86|SME}} |
| + | * {{x86|SMM}} |
| + | * {{x86|SMX}} |
| + | * {{x86|SSE}} |
| + | * {{x86|SSE2}} |
| + | * {{x86|SSE3}} |
| + | * {{x86|SSE4.1}} |
| + | * {{x86|SSE4.2}} |
| + | * {{x86|SSE4a}} |
| + | * {{x86|SSE5}} |
| + | * {{x86|SSSE3}} |
| + | * {{x86|TBM}} |
| + | * {{x86|TME}} |
| + | * {{x86|TSME}} |
| + | * {{x86|TSX}} |
| + | * {{x86|XOP}} |
| + | </div>{{Navbar|Template:x86 isa main|text=|mini=1|style=float:right;}} |
| + | </div> |