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{{chip
 
{{chip
 
|name=Exynos Auto V9
 
|name=Exynos Auto V9
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|image=exynos auto v9 (back).png
+
|image=exynos auto v9 (front).png
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|back image=exynos auto v9 (front).png
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|back image=exynos auto v9 (back).png
 
|designer=Samsung
 
|designer=Samsung
 
|designer 2=ARM Holdings
 
|designer 2=ARM Holdings
Line 16: Line 16:
 
|microarch=Cortex-A76
 
|microarch=Cortex-A76
 
|core name=Cortex-A76
 
|core name=Cortex-A76
 +
|process=8 nm
 
|technology=CMOS
 
|technology=CMOS
 
|word size=64 bit
 
|word size=64 bit
Line 21: Line 22:
 
|thread count=8
 
|thread count=8
 
}}
 
}}
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'''Exynos Auto V9''' is a {{arch|64}} [[octa-core]] [[ARM]] SoC introduced by [[Samsung]] for automotive infotainment applications. Fabricated on Samsung's own [[8 nm process]], the V9 features eight {{armh|Cortex-A76|l=arch}} cores and a [[safety island]] core that supports Automotive Safety Integrity Level (ASIL)-B standards. This chip integrates the [[Mali G76]] GPU as well as a [[neural processing unit]].
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'''Exynos Auto V9''' is a {{arch|64}} [[octa-core]] [[ARM]] SoC introduced by [[Samsung]] for automotive infotainment applications. Fabricated on Samsung's own [[8 nm process]], the V9 features eight {{armh|Cortex-A76|l=arch}} cores operating at up to 2.1 GHz and a [[safety island]] core that supports Automotive Safety Integrity Level (ASIL)-B standards. This chip integrates the [[Mali G76]] GPU as well as a [[neural processing unit]].
 +
 
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== Cache ==
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{{main|arm holdings/microarchitectures/cortex-a76#Memory_Hierarchy|l1=Cortex-A76 § Cache}}
 +
{{cache size
 +
|l1 cache=1 MiB
 +
|l1i cache=512 KiB
 +
|l1i break=8x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=512 KiB
 +
|l1d break=8x64 KiB
 +
|l1d desc=4-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=2-4? MiB
 +
|l2 break=8x256/512 KiB
 +
|l2 desc=8-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=? MiB
 +
|l3 break=2x? MiB
 +
|l3 desc=16-way set associative
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=LPDDR4-????
 +
|type 2=LPDDR5-????
 +
}}
 +
 
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = Mali-G76
 +
| device id          =
 +
| designer            = ARM Holdings
 +
| execution units    = ?
 +
| max displays        = 6
 +
| max memory          =
 +
| frequency          = ?
 +
 
 +
| direct3d ver        = 12
 +
| opencl ver          = 2.0
 +
| opengl ver          = 3.2
 +
| opengl es ver      = 3.2
 +
| vulkan ver          = 1.1
 +
| openvg ver          = 1.1
 +
}}
  
 
== Audio ==
 
== Audio ==
 
* [[Tensilica]] HiFi 4 DSP
 
* [[Tensilica]] HiFi 4 DSP

Latest revision as of 12:26, 30 May 2020

Edit Values
Exynos Auto V9
exynos auto v9 (front).png
General Info
DesignerSamsung,
ARM Holdings
ManufacturerSamsung
Model NumberV9
IntroductionJanuary 3, 2018 (announced)
January 3, 2018 (launched)
General Specs
FamilyExynos Auto
Frequency2.1 GHz
Microarchitecture
ISAARMv8.2 (ARM)
MicroarchitectureCortex-A76
Core NameCortex-A76
Process8 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Packaging
exynos auto v9 (back).png

Exynos Auto V9 is a 64-bit octa-core ARM SoC introduced by Samsung for automotive infotainment applications. Fabricated on Samsung's own 8 nm process, the V9 features eight Cortex-A76 cores operating at up to 2.1 GHz and a safety island core that supports Automotive Safety Integrity Level (ASIL)-B standards. This chip integrates the Mali G76 GPU as well as a neural processing unit.

Cache[edit]

Main article: Cortex-A76 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1 MiB
1,024 KiB
1,048,576 B
L1I$512 KiB
524,288 B
0.5 MiB
8x64 KiB4-way set associative 
L1D$512 KiB
524,288 B
0.5 MiB
8x64 KiB4-way set associativewrite-back
L2$2-4? MiB
"-4?MiB" is not declared as a valid unit of measurement for this property.
  8x256/512 KiB8-way set associativewrite-back
L3$? MiB
"? MiB" is not a number.
  2x? MiB16-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4-????, LPDDR5-????

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G76
DesignerARM Holdings
Execution Units?
"?" is not a number.
Max Displays6
Frequency?
"?" is not a number.
Standards
Direct3D12
OpenGL3.2
OpenCL2.0
OpenGL ES3.2
OpenVG1.1
Vulkan1.1

Audio[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/exynos_auto/v9&oldid=97141"
Facts about "Exynos Auto V9 - Samsung"
RDF feed
back imageFile:exynos auto v9 (back).png +
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
core count8 +
core nameCortex-A76 +
designerSamsung + and ARM Holdings +
familyExynos Auto +
first announcedJanuary 3, 2018 +
first launchedJanuary 3, 2018 +
full page namesamsung/exynos auto/v9 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuMali-G76 +
integrated gpu designerARM Holdings +
isaARMv8.2 +
isa familyARM +
l1$ size1,024 KiB (1,048,576 B, 1 MiB) +
l1d$ description4-way set associative +
l1d$ size512 KiB (524,288 B, 0.5 MiB) +
l1i$ description4-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description8-way set associative +
l3$ description16-way set associative +
ldateJanuary 3, 2018 +
main imageFile:exynos auto v9 (front).png +
manufacturerSamsung +
microarchitectureCortex-A76 +
model numberV9 +
nameExynos Auto V9 +
process8 nm (0.008 μm, 8.0e-6 mm) +
supported memory typeLPDDR4-???? + and LPDDR5-???? +
technologyCMOS +
thread count8 +
word size64 bit (8 octets, 16 nibbles) +