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{{intel title|Ice Lake (server)|arch}}
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{{microarchitecture
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|atype=CPU
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|name=Ice Lake (server)
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|designer=Intel
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|manufacturer=Intel
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|introduction=2020
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|process=10 nm
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|isa=x86-64
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|core name=Ice Lake SP
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|core name 2=Ice Lake X
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|predecessor=Cooper Lake
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|predecessor link=intel/microarchitectures/cooper lake
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|successor=Sapphire Rapids
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|successor link=intel/microarchitectures/sapphire rapids
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|contemporary=Ice Lake (client)
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|contemporary link=intel/microarchitectures/ice_lake_(client)
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}}
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'''Ice Lake''' ('''ICL''', '''ICX''') '''Server Configuration''' is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[10 nm]] [[microarchitecture]] for enthusiasts and servers.
  
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== Codenames ==
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{| class="wikitable"
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|-
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! Core !! Abbrev !! Target
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|-
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| {{intel|Ice Lake X|l=core}} || ICL-X || High-end desktops & enthusiasts market
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|-
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| {{intel|Ice Lake W|l=core}} || ICL-W || Enterprise/Business workstations
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|-
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| {{intel|Ice Lake SP|l=core}} || ICL-SP || Server Scalable Processors
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|}
 +
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== Release Dates ==
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[[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|{{\\|Cooper Lake}} and Ice Lake roadmap.]]
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Ice Lake server processors are said to launch in the first half of 2020.
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== Process Technology==
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{{see also|intel/microarchitectures/ice lake (client)#Process_Technology|l1=Ice Lake (client) § Process Technology}}
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Ice Lake will use a second-generation enhanced [[10 nm process]] called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.
 +
 +
== Compiler support ==
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Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.
 +
{| class="wikitable"
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|-
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! Compiler !! Arch-Specific || Arch-Favorable
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|-
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| [[ICC]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code>
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|-
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| [[GCC]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code>
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|-
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| [[LLVM]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code>
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|-
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| [[Visual Studio]] || <code>/?</code> || <code>/tune:?</code>
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|}
 +
 +
=== CPUID ===
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{| class="wikitable tc1 tc2 tc3 tc4"
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! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
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|-
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| rowspan="2" | ? || 0 || 0x6 || 0x? || ?
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|-
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| colspan="4" | Family 6 Model ?
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|-
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| rowspan="2" | ? || 0 || 0x6 || ? || ?
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|-
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| colspan="4" | Family 6 Model ?
 +
|}
 +
 +
== Architecture ==
 +
 +
=== Key changes from {{\\|Cascade Lake}}===
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* Enhanced "10nm+" (from [[14 nm]])
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* {{\\|Sunny Cove|Sunny Cove core}}
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** ''See {{\\|Sunny Cove}} for microarchitectural details and changes''
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* I/O
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** PCIe 4.0 (from PCIe 3.0)
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* Memory
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** Higher bandwidth (190.7 GiB/s, up from 143.1 GiB/s)
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** Octa-channel (up from hexa-channel)
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** 3200 MT/s (up from 2933 MT/s)
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** Optane DC DIMMs
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*** Apache Pass '''→''' Barlow Pass
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* Platform
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** {{intel|Purley|l=platform}} '''→''' {{intel|Whitley|l=platform}}
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* Packaging
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** 4189-contact flip-chip LGA (up from 3647 contacts)
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{{expand list}}
 +
 +
====New instructions ====
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Ice Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|Sunny cove#New instructions|Sunny Cove § New Instructions|l=arch}} for details.
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 +
== All Ice Lake Chips ==
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{{future information}}
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<!-- NOTE:
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          This table is generated automatically from the data in the actual articles.
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          If a microprocessor is missing from the list, an appropriate article for it needs to be
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          created and tagged accordingly.
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          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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-->
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{{comp table start}}
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<table class="comptable sortable tc6 tc7 tc14 tc15">
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="24">List of Ice Lake Processors</th></tr>
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="2">Frequency/{{intel|Turbo Boost|Turbo}}</th><th>Mem</th><th colspan="7">Major Feature Diff</th></tr>
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{{comp table header 1|cols=Launched, Price, Family, Core Name, Cores, Threads, %L2$, %L3$, TDP, %Frequency, %Max Turbo, Max Mem, Turbo, SMT}}
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<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Uniprocessors]]</th></tr>
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{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]] [[max cpu count::1]]
 +
|?full page name
 +
|?model number
 +
|?first launched
 +
|?release price
 +
|?microprocessor family
 +
|?core name
 +
|?core count
 +
|?thread count
 +
|?l2$ size
 +
|?l3$ size
 +
|?tdp
 +
|?base frequency#GHz
 +
|?turbo frequency (1 core)#GHz
 +
|?max memory#GiB
 +
|?has intel turbo boost technology 2_0
 +
|?has simultaneous multithreading
 +
|format=template
 +
|template=proc table 3
 +
|searchlabel=
 +
|sort=microprocessor family, model number
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|order=asc,asc
 +
|userparam=16:15
 +
|mainlabel=-
 +
|limit=200
 +
}}
 +
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Multiprocessors]] (2-way)</th></tr>
 +
{{#ask:
 +
[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]] [[max cpu count::2]]
 +
|?full page name
 +
|?model number
 +
|?first launched
 +
|?release price
 +
|?microprocessor family
 +
|?core name
 +
|?core count
 +
|?thread count
 +
|?l2$ size
 +
|?l3$ size
 +
|?tdp
 +
|?base frequency#GHz
 +
|?turbo frequency (1 core)#GHz
 +
|?max memory#GiB
 +
|?has intel turbo boost technology 2_0
 +
|?has simultaneous multithreading
 +
|format=template
 +
|template=proc table 3
 +
|searchlabel=
 +
|sort=microprocessor family, model number
 +
|order=asc,asc
 +
|userparam=16:15
 +
|mainlabel=-
 +
|limit=60
 +
}}
 +
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Multiprocessors]] (4-way)</th></tr>
 +
{{#ask:
 +
[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]] [[max cpu count::4]]
 +
|?full page name
 +
|?model number
 +
|?first launched
 +
|?release price
 +
|?microprocessor family
 +
|?core name
 +
|?core count
 +
|?thread count
 +
|?l2$ size
 +
|?l3$ size
 +
|?tdp
 +
|?base frequency#GHz
 +
|?turbo frequency (1 core)#GHz
 +
|?max memory#GiB
 +
|?has intel turbo boost technology 2_0
 +
|?has simultaneous multithreading
 +
|format=template
 +
|template=proc table 3
 +
|searchlabel=
 +
|sort=microprocessor family, model number
 +
|order=asc,asc
 +
|userparam=16:15
 +
|mainlabel=-
 +
|limit=60
 +
}}
 +
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Multiprocessors]] (8-way)</th></tr>
 +
{{#ask:
 +
[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]] [[max cpu count::8]]
 +
|?full page name
 +
|?model number
 +
|?first launched
 +
|?release price
 +
|?microprocessor family
 +
|?core name
 +
|?core count
 +
|?thread count
 +
|?l2$ size
 +
|?l3$ size
 +
|?tdp
 +
|?base frequency#GHz
 +
|?turbo frequency (1 core)#GHz
 +
|?max memory#GiB
 +
|?has intel turbo boost technology 2_0
 +
|?has simultaneous multithreading
 +
|format=template
 +
|template=proc table 3
 +
|searchlabel=
 +
|sort=microprocessor family, model number
 +
|order=asc,asc
 +
|userparam=16:15
 +
|mainlabel=-
 +
|limit=60
 +
}}
 +
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]]}}
 +
</table>
 +
{{comp table end}}

Revision as of 23:05, 23 March 2020

Edit Values
Ice Lake (server) µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2020
Process10 nm
Instructions
ISAx86-64
Cores
Core NamesIce Lake SP,
Ice Lake X
Succession
Contemporary
Ice Lake (client)

Ice Lake (ICL, ICX) Server Configuration is Intel's successor to Cascade Lake, a 10 nm microarchitecture for enthusiasts and servers.

Codenames

Core Abbrev Target
Ice Lake X ICL-X High-end desktops & enthusiasts market
Ice Lake W ICL-W Enterprise/Business workstations
Ice Lake SP ICL-SP Server Scalable Processors

Release Dates

Cooper Lake and Ice Lake roadmap.

Ice Lake server processors are said to launch in the first half of 2020.

Process Technology

See also: Ice Lake (client) § Process Technology

Ice Lake will use a second-generation enhanced 10 nm process called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.

Compiler support

Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.

Compiler Arch-Specific Arch-Favorable
ICC -march=icelake-server -mtune=icelake-server
GCC -march=icelake-server -mtune=icelake-server
LLVM -march=icelake-server -mtune=icelake-server
Visual Studio /? /tune:?

CPUID

Core Extended
Family 		Family Extended
Model 		Model
 ? 0 0x6 0x?  ?
Family 6 Model ?
 ? 0 0x6  ?  ?
Family 6 Model ?

Architecture

Key changes from Cascade Lake

  • Enhanced "10nm+" (from 14 nm)
  • Sunny Cove core
    • See Sunny Cove for microarchitectural details and changes
  • I/O
    • PCIe 4.0 (from PCIe 3.0)
  • Memory
    • Higher bandwidth (190.7 GiB/s, up from 143.1 GiB/s)
    • Octa-channel (up from hexa-channel)
    • 3200 MT/s (up from 2933 MT/s)
    • Optane DC DIMMs
      • Apache Pass → Barlow Pass
  • Platform
  • Packaging
    • 4189-contact flip-chip LGA (up from 3647 contacts)

This list is incomplete; you can help by expanding it.

New instructions

Ice Lake introduced a number of new instructions. See Sunny Cove § New Instructions for details.

All Ice Lake Chips

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
 List of Ice Lake Processors
 Main processorFrequency/TurboMemMajor Feature Diff
ModelLaunchedPriceFamilyCore NameCoresThreadsL2$L3$TDPFrequencyMax TurboMax MemTurboSMT
 Uniprocessors
 Multiprocessors (2-way)
 Multiprocessors (4-way)
 Multiprocessors (8-way)
Count: 0
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/ice_lake_(server)&oldid=96480"
Facts about "Ice Lake (server) - Microarchitectures - Intel"
RDF feed
codenameIce Lake (server) +
designerIntel +
first launched2020 +
full page nameintel/microarchitectures/ice lake (server) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameIce Lake (server) +
process10 nm (0.01 μm, 1.0e-5 mm) +