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{{intel title|Cooper Lake|arch}}
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{{microarchitecture
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|atype=CPU
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|name=Cooper Lake
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|designer=Intel
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|manufacturer=Intel
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|introduction=2019
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|process=14 nm
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|type=Superscalar
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|oooe=Yes
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|speculative=Yes
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|renaming=Yes
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|stages min=14
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|stages max=19
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|isa=x86-64
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|extension=MOVBE
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|extension 2=MMX
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|extension 3=SSE
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|extension 4=SSE2
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|extension 5=SSE3
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|extension 6=SSSE3
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|extension 7=SSE4.1
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|extension 8=SSE4.2
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|extension 9=POPCNT
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|extension 10=AVX
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|extension 11=AVX2
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|extension 12=AES
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|extension 13=PCLMUL
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|extension 14=FSGSBASE
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|extension 15=RDRND
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|extension 16=FMA3
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|extension 17=F16C
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|extension 18=BMI
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|extension 19=BMI2
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|extension 20=VT-x
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|extension 21=VT-d
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|extension 22=TXT
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|extension 23=TSX
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|extension 24=RDSEED
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|extension 25=ADCX
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|extension 26=PREFETCHW
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|extension 27=CLFLUSHOPT
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|extension 28=XSAVE
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|extension 29=SGX
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|extension 30=MPX
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|extension 31=AVX-512
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|l1i=32 KiB
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|l1i per=core
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|l1i desc=8-way set associative
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|l1d=32 KiB
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|l1d per=core
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|l1d desc=8-way set associative
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|l2=1 MiB
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|l2 per=core
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|l2 desc=16-way set associative
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|l3=1.375 MiB
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|l3 per=core
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|l3 desc=11-way set associative
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|core name=Cooper Lake X
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|core name 2=Cooper Lake SP
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|core name 3=Cooper Lake AP
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|predecessor=Cascade Lake
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|predecessor link=intel/microarchitectures/cascade lake
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|successor=Ice Lake (Server)
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|successor link=intel/microarchitectures/ice lake (server)
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|contemporary=Coffee Lake
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|contemporary link=intel/microarchitectures/coffee lake
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}}
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'''Cooper Lake''' ('''CPL''') is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[14 nm]] [[microarchitecture]] for enthusiasts and servers.
  
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For desktop enthusiasts, Cascade Lake is branded {{intel|Core i7}}, and {{intel|Core i9}} processors (under the {{intel|Core X}} series). For scalable server class processors, Intel branded it as {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}}.
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== Codenames ==
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{| class="wikitable"
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|-
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! Core !! Abbrev !! Target
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|-
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| {{intel|Cooper Lake X|l=core}} || CPL-X || High-end desktops & enthusiasts market
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|-
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| {{intel|Cooper Lake W|l=core}} || CPL-W || Enterprise/Business workstations
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|-
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| {{intel|Cooper Lake SP|l=core}} || CPL-SP || Server Scalable Processors
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|-
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| {{intel|Cooper Lake AP|l=core}} || CPL-AP || Server Advanced Processors
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|}
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== Brands ==
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{{empty section}}
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== Release Dates ==
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[[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|Cooper Lake and {{\\|Ice Lake}} roadmap.]]
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Cooper Lake is expected to be released in the first half of 2020.
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== Process Technology ==
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Cooper Lake is fabricated on Intel's 3rd generation enhanced [[14 nm process|14nm++ process]].
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== Architecture ==
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Cooper Lake is based on the {{intel|Whitley|l=platform}} platform.
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=== Key changes from {{\\|Cascade Lake}} ===
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{{future information}}
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* SoC
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** Mainstream 56 cores (up from 28) (note that {{intel|Cascade Lake AP|l=core}} already offered up to 56 cores)
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*** Socketed (from soldered and only sold as part of the S9200WK module)
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** 3-die multi-chip package (up from a single monolithic die)
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* Memory
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** Higher bandwidth (174.84 GiB/s, up from 119.209 GiB/s)
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** Octa-channel (up from hexa-channel)
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** Optane DC DIMMs
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*** Apache Pass '''→''' Barlow Pass
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* Platform
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** {{intel|Purley|l=platform}} '''→''' {{intel|Whitley|l=platform}} (mainstream)
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** {{intel|Walker Pass|l=platform}} '''→''' {{intel|Cedar Island|l=platform}} (AP)
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* Packaging
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** 4189-contact flip-chip LGA (up from 3647 contacts)
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{{expand list}}
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====New instructions ====
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Cooper Lake introduced a number of {{x86|extensions|new instructions}}:
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* [[BFLOAT16]] - A new data type for [[acceleration]] of [[neural processor|AI workloads]].
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* {{x86|AVX512 BF16}} - AVX-512 [[Brain Float 16]] extension
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== See also ==
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* {{\\|Ice Lake (Server)}}

Revision as of 23:05, 23 March 2020

Edit Values
Cooper Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2019
Process14 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache1 MiB/core
16-way set associative
L3 Cache1.375 MiB/core
11-way set associative
Cores
Core NamesCooper Lake X,
Cooper Lake SP,
Cooper Lake AP
Succession
Contemporary
Coffee Lake

Cooper Lake (CPL) is Intel's successor to Cascade Lake, a 14 nm microarchitecture for enthusiasts and servers.

For desktop enthusiasts, Cascade Lake is branded Core i7, and Core i9 processors (under the Core X series). For scalable server class processors, Intel branded it as Xeon Bronze, Xeon Silver, Xeon Gold, and Xeon Platinum.


Codenames

Core Abbrev Target
Cooper Lake X CPL-X High-end desktops & enthusiasts market
Cooper Lake W CPL-W Enterprise/Business workstations
Cooper Lake SP CPL-SP Server Scalable Processors
Cooper Lake AP CPL-AP Server Advanced Processors

Brands

New text document.svg This section is empty; you can help add the missing info by editing this page.

Release Dates

Cooper Lake and Ice Lake roadmap.

Cooper Lake is expected to be released in the first half of 2020.

Process Technology

Cooper Lake is fabricated on Intel's 3rd generation enhanced 14nm++ process.

Architecture

Cooper Lake is based on the Whitley platform.

Key changes from Cascade Lake

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
  • SoC
    • Mainstream 56 cores (up from 28) (note that Cascade Lake AP already offered up to 56 cores)
      • Socketed (from soldered and only sold as part of the S9200WK module)
    • 3-die multi-chip package (up from a single monolithic die)
  • Memory
    • Higher bandwidth (174.84 GiB/s, up from 119.209 GiB/s)
    • Octa-channel (up from hexa-channel)
    • Optane DC DIMMs
      • Apache Pass → Barlow Pass
  • Platform
  • Packaging
    • 4189-contact flip-chip LGA (up from 3647 contacts)

This list is incomplete; you can help by expanding it.

New instructions

Cooper Lake introduced a number of new instructions:

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/cooper_lake&oldid=96473"
Facts about "Cooper Lake - Microarchitectures - Intel"
RDF feed
codenameCooper Lake +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/cooper lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCooper Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +