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Difference between revisions of "intel/microarchitectures/willow cove"
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{{intel title|Willow Cove|arch}}
 
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{{microarchitecture
 
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|atype=CPU
 
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|name=Willow Cove
 
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|designer=Intel
 
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|manufacturer=Intel
 
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|introduction=2020
 
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|process=10 nm
 
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|isa=x86-64
 
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|predecessor=Sunny Cove
 
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|predecessor link=intel/microarchitectures/sunny cove
 
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|successor=Golden Cove
 
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|successor link=intel/microarchitectures/golden cove
 
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}}
 
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'''Willow Cove''' is the successor to {{\\|Sunny Cove}}, a high-performance [[10 nm]] [[x86]] core microarchitecture designed by [[Intel]] for an array of server and client products, including {{\\|Tiger Lake}}.
 
  
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== History ==
 
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[[File:sunny cove roadmap.png|thumb|right|400px|Intel Core roadmap]]
 
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Willow Cove was originally unveiled by Intel at their 2018 architecture day. Willow Cove is intended to succeed Sunny Cove in the 2020 timeframe.
 
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== Process Technology ==
 
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Willow Cove is designed to take advantage of Intel's [[10 nm process]].
 
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== Architecture ==
 
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=== Key changes from {{\\|Sunny Cove}}===
 
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* New cache subsystem
 
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* Security features
 
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{{expand list}}
 
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==== New instructions ====
 
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Willow Cove introduced a number of {{x86|extensions|new instructions}}:
 
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* Control-flow Enforcement Technology (CET) enhancements
 
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* {{x86|MOVDIR|<code>MOVDIR</code>}} - Direct stores
 
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* Additional {{x86|AVX-512}} extensions:
 
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** {{x86|AVX512_VP2INTERSECT|<code>AVX512_VP2INTERSECT</code>}} -  AVX-512 Vector Intersection Instructions
 
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''Only on server parts ({{\\|Sapphire Rapids}}):''
 
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* {{x86|ENQCMD|<code>ENQCMD</code>}} - Enqueue Stores
 
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== Bibliography ==
 
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* Intel Architecture Day 2018, December 11, 2018
 

Revision as of 17:45, 23 March 2020

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Facts about "Willow Cove - Microarchitectures - Intel"
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codenameWillow Cove +
core count2 +, 4 +, 6 + and 8 +
designerIntel +
first launched2020 +
full page nameintel/microarchitectures/willow cove +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameWillow Cove +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +