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Difference between revisions of "intel/cores/cascade lake r"
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|tech=CMOS | |tech=CMOS | ||
|package name 1=intel,fclga_3647 | |package name 1=intel,fclga_3647 | ||
| − | |predecessor= | + | |predecessor=Skylake SP |
| − | |predecessor link=intel/cores/ | + | |predecessor link=intel/cores/skylake sp |
|successor=Ice Lake SP | |successor=Ice Lake SP | ||
|successor link=intel/cores/ice lake sp | |successor link=intel/cores/ice lake sp | ||
| + | |contemporary=Cascade Lake SP | ||
| + | |contemporary link=intel/cores/cascade lake sp | ||
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'''Cascade Lake R''' ('''{{intel|Cascade Lake|l=arch}} Scalable Performance Refresh''') is code name for Intel's series of server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform serving as mid-cycle refresh to {{intel|Cascade Lake SP|l=core}}. Cascade Lake R only targets mainstream entry and mid-range servers and therefore only support up to 2-way multiprocessing. As with {{\\|Cascade Lake SP}}, these chips also support up to [[28 cores]], incorporate {{x86|AVX512-VNNI|AVX512}} [[x86]] {{x86|extension}} for neural network / deep learning workloads, and introduces [[persistent memory]] support. Cascade Lake R-based chips are manufactured on an enhanced [[14 nm process]] and utilize the {{intel|Lewisburg|l=chipset}} chipset. | '''Cascade Lake R''' ('''{{intel|Cascade Lake|l=arch}} Scalable Performance Refresh''') is code name for Intel's series of server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform serving as mid-cycle refresh to {{intel|Cascade Lake SP|l=core}}. Cascade Lake R only targets mainstream entry and mid-range servers and therefore only support up to 2-way multiprocessing. As with {{\\|Cascade Lake SP}}, these chips also support up to [[28 cores]], incorporate {{x86|AVX512-VNNI|AVX512}} [[x86]] {{x86|extension}} for neural network / deep learning workloads, and introduces [[persistent memory]] support. Cascade Lake R-based chips are manufactured on an enhanced [[14 nm process]] and utilize the {{intel|Lewisburg|l=chipset}} chipset. | ||
Cascade Lake R-based models are branded as the 2nd-generation {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, and {{intel|Xeon Gold}} [[processor families]]. | Cascade Lake R-based models are branded as the 2nd-generation {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, and {{intel|Xeon Gold}} [[processor families]]. | ||
Revision as of 13:26, 27 February 2020
| Edit Values | |
| Cascade Lake SP | |
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| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | February 24, 2020 (announced) February 24, 2020 (launched) |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Cascade Lake |
| Platform | Purley |
| Chipset | Lewisburg |
| Word Size | 8 octets 64 bit16 nibbles |
| Process | 14 nm 0.014 μm 1.4e-5 mm |
| Technology | CMOS |
| Packaging | |
| Package | FCLGA-3647 (FCLGA) |
| Dimension | 76.16 mm × 56.6 mm |
| Pitch | 0.8585 mm × 0.9906 mm |
| Contacts | 3647 |
| Socket | Socket P, LGA-3647 |
| Succession | |
| Contemporary | |
| Cascade Lake SP | |
Cascade Lake R (Cascade Lake Scalable Performance Refresh) is code name for Intel's series of server multiprocessors based on the Cascade Lake microarchitecture as part of the Purley platform serving as mid-cycle refresh to Cascade Lake SP. Cascade Lake R only targets mainstream entry and mid-range servers and therefore only support up to 2-way multiprocessing. As with Cascade Lake SP, these chips also support up to 28 cores, incorporate AVX512 x86 extension for neural network / deep learning workloads, and introduces persistent memory support. Cascade Lake R-based chips are manufactured on an enhanced 14 nm process and utilize the Lewisburg chipset.
Cascade Lake R-based models are branded as the 2nd-generation Xeon Bronze, Xeon Silver, and Xeon Gold processor families.
Facts about "Cascade Lake R - Cores - Intel"
| chipset | Lewisburg + |
| designer | Intel + |
| first announced | February 24, 2020 + |
| first launched | February 24, 2020 + |
| instance of | core + |
| isa | x86-64 + |
| isa family | x86 + |
| main image | + |
| manufacturer | Intel + |
| microarchitecture | Cascade Lake + |
| name | Cascade Lake SP + |
| package | FCLGA-3647 + |
| platform | Purley + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| socket | Socket P + and LGA-3647 + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |
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