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Difference between revisions of "intel/microarchitectures/tiger lake"
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|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
− | |introduction= | + | |introduction=2020 |
|process=10 nm | |process=10 nm | ||
|isa=x86-64 | |isa=x86-64 | ||
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== Process Technology== | == Process Technology== | ||
{{main|intel/microarchitectures/cannon lake#Process_Technology|l1=Cannon Lake § Process Technology}} | {{main|intel/microarchitectures/cannon lake#Process_Technology|l1=Cannon Lake § Process Technology}} | ||
− | Tiger Lake | + | Tiger Lake will be manufactured on Intel's third generation enhanced [[10 nm process|10nm++ process]]. |
+ | |||
+ | == History == | ||
+ | [[File:intel 2019 investor meeting tiger lake roadmap.png|right|thumb|Intel 2019 and 2020 Roadmap]] | ||
+ | Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2020. | ||
== Architecture == | == Architecture == | ||
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=== Key changes from {{\\|Ice Lake}}=== | === Key changes from {{\\|Ice Lake}}=== | ||
− | {{ | + | * Core |
− | + | ** {{\\|Sunny Cove}} '''➡''' {{\\|Willow Cove}} | |
− | * {{intel|Gen11|l=arch}} | + | ** Up to 50% larger Level 3 cache - 3MB per core from 2MB per core |
+ | * GPU | ||
+ | ** {{intel|Gen11|l=arch}} '''➡''' {{intel|Gen12|l=arch}} (Xe) | ||
+ | ** 1.5x more EUs (96, up from 64) | ||
+ | * Display | ||
+ | ** [[HDMI]] 2.1 (from HDMI 2.0b) | ||
+ | * I/O | ||
+ | ** PCIe 4.0 (from 3.0) |
Revision as of 12:11, 17 December 2019
Edit Values | |
Tiger Lake µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | 2020 |
Process | 10 nm |
Instructions | |
ISA | x86-64 |
Succession | |
Contemporary | |
Sapphire Rapids |
Tiger Lake (TGL) is Intel's successor to Ice Lake, a 10nm microarchitecture for mainstream workstations, desktops, and mobile devices.
Process Technology
- Main article: Cannon Lake § Process Technology
Tiger Lake will be manufactured on Intel's third generation enhanced 10nm++ process.
History
Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2020.
Architecture
Not much is known about Tiger Lake's architecture.
Key changes from Ice Lake
- Core
- Sunny Cove ➡ Willow Cove
- Up to 50% larger Level 3 cache - 3MB per core from 2MB per core
- GPU
- Display
- HDMI 2.1 (from HDMI 2.0b)
- I/O
- PCIe 4.0 (from 3.0)
Facts about "Tiger Lake - Microarchitectures - Intel"
codename | Tiger Lake + |
designer | Intel + |
first launched | 2020 + |
full page name | intel/microarchitectures/tiger lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Tiger Lake + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |