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{{pezy title|PEZY-SC3}} | {{pezy title|PEZY-SC3}} | ||
− | {{ | + | {{chip |
|future=Yes | |future=Yes | ||
|name=PEZY-SC3 | |name=PEZY-SC3 | ||
Line 9: | Line 9: | ||
|market=Supercomputer | |market=Supercomputer | ||
|first announced=2016 | |first announced=2016 | ||
− | |first launched= | + | |first launched=2019 |
− | |frequency=1,333 MHz | + | |family=PEZY-SCx |
+ | |frequency=1,333.333 MHz | ||
|process=7 nm | |process=7 nm | ||
|technology=CMOS | |technology=CMOS | ||
|die area=700 mm² | |die area=700 mm² | ||
− | |core count=8, | + | |core count=8,192 |
+ | |thread count=65,536 | ||
|power=400 W | |power=400 W | ||
|v core=0.65 V | |v core=0.65 V | ||
}} | }} | ||
− | '''PEZY-SC3''' ('''PEZY Super Computer 3''') is fourth generation [[many-core microprocessor]] | + | '''PEZY-SC3''' ('''PEZY Super Computer 3''') is a fourth generation [[many-core microprocessor]] developed by [[PEZY]] set to be introduced in late 2019. This chip, which is planned to operate at 1.3 GHz, will incorporate 8,192 cores and dissipate 400 W. The PEZY-SC3 will power the [[ZettaScaler]]-3.x series of supercomputers. |
− | |||
+ | {{unknown features}} | ||
+ | |||
+ | |||
+ | == Overview == | ||
+ | The SC3 will be introduced by [[PEZY]] along with their third-generation [[ZettaScaler]]-3.0 supercomputer series. The SC3 is set to incorporate 8,192 cores along with 8-way [[simultaneous multithreading|SMT]] support for a total of 65,536 threads, four times as many cores as {{\\|PEZY-SC2|its predecessor}}. | ||
− | {{ | + | Operating at 1.3 GHz, the PEZY-SC3 will have a peak performance of 43.69 [[TFLOPS]] (single-precision) and 21.845 TFLOPS (double-precision) while consuming around 400 Watts. The PEZY-SC3 is expected to be manufactured on [[TSMC]]'s [[7 nm process]]. |
+ | {{#set: | ||
+ | | peak flops (half-precision) = {{#expr:1333333333 * 8 * 8192}} FLOPS | ||
+ | | peak flops (single-precision) = {{#expr:1333333333 * 4 * 8192}} FLOPS | ||
+ | | peak flops (double-precision) = {{#expr:1333333333 * 2 * 8192}} FLOPS | ||
+ | }} | ||
+ | == Cache == | ||
+ | {{empty section}} | ||
== Memory controller == | == Memory controller == | ||
+ | For main memory, the PEZY-SC3 supports 4 channels of 64-bit DDR4-3600 memory with ECC support for a total aggregated bandwidth of 107.3 GiB/s | ||
{{memory controller | {{memory controller | ||
|type=DDR4-3600 | |type=DDR4-3600 | ||
Line 31: | Line 45: | ||
|controllers=4 | |controllers=4 | ||
|channels=4 | |channels=4 | ||
+ | |width=64 bit | ||
|max bandwidth=107.3 GiB/s | |max bandwidth=107.3 GiB/s | ||
+ | |bandwidth schan=26.82 GiB/s | ||
+ | |bandwidth dchan=53.64 GiB/s | ||
|bandwidth qchan=107.3 GiB/s | |bandwidth qchan=107.3 GiB/s | ||
}} | }} | ||
+ | |||
+ | In addition to main memory bandwidth, the PEZY-SC3 supports Wide-IO with a width of 2,048 bit, twice of the {{\\|PEZY-SC2|SC2}}. As with the SC2, the SC3 will use [[ThruChip Interface]] (TCI) interfaces in order to communicate with the TCI-DRAM chips. This chip incorporates 8 interfaces, operating at 3 GHz for a bandwidth of 1.525 TB/s per interface for a total aggregated bandwidth of 12.2 TB/s - over 5.8 the bandwidth of its predecessor. | ||
{{memory controller | {{memory controller | ||
− | |wide-io clock= | + | |wide-io clock=3,000 MHz |
− | |wide-io width= | + | |wide-io width=2,048 bit |
|channels=8 | |channels=8 | ||
|max bandwidth=11.18 TiB/s | |max bandwidth=11.18 TiB/s | ||
}} | }} | ||
− | |||
== Expansions == | == Expansions == | ||
− | {{ | + | With the SC3, PEZY plans to replace {{\\|PEZY-SC2|the previous}} PCIe interface with a custom optics interface featuring 128 lanes supporting a bandwidth of 256 GB/s. |
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− | |||
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− | }} |
Latest revision as of 12:41, 28 September 2019
Edit Values | |
PEZY-SC3 | |
General Info | |
Designer | PEZY |
Manufacturer | TSMC |
Model Number | PEZY-SC3 |
Market | Supercomputer |
Introduction | 2016 (announced) 2019 (launched) |
General Specs | |
Family | PEZY-SCx |
Frequency | 1,333.333 MHz |
Microarchitecture | |
Process | 7 nm |
Technology | CMOS |
Die | 700 mm² |
Cores | 8,192 |
Threads | 65,536 |
Electrical | |
Power dissipation | 400 W |
Vcore | 0.65 V |
PEZY-SC3 (PEZY Super Computer 3) is a fourth generation many-core microprocessor developed by PEZY set to be introduced in late 2019. This chip, which is planned to operate at 1.3 GHz, will incorporate 8,192 cores and dissipate 400 W. The PEZY-SC3 will power the ZettaScaler-3.x series of supercomputers.
Contents
Overview[edit]
The SC3 will be introduced by PEZY along with their third-generation ZettaScaler-3.0 supercomputer series. The SC3 is set to incorporate 8,192 cores along with 8-way SMT support for a total of 65,536 threads, four times as many cores as its predecessor.
Operating at 1.3 GHz, the PEZY-SC3 will have a peak performance of 43.69 TFLOPS (single-precision) and 21.845 TFLOPS (double-precision) while consuming around 400 Watts. The PEZY-SC3 is expected to be manufactured on TSMC's 7 nm process.
Cache[edit]
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This section is empty; you can help add the missing info by editing this page. |
Memory controller[edit]
For main memory, the PEZY-SC3 supports 4 channels of 64-bit DDR4-3600 memory with ECC support for a total aggregated bandwidth of 107.3 GiB/s
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Integrated Memory Controller
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In addition to main memory bandwidth, the PEZY-SC3 supports Wide-IO with a width of 2,048 bit, twice of the SC2. As with the SC2, the SC3 will use ThruChip Interface (TCI) interfaces in order to communicate with the TCI-DRAM chips. This chip incorporates 8 interfaces, operating at 3 GHz for a bandwidth of 1.525 TB/s per interface for a total aggregated bandwidth of 12.2 TB/s - over 5.8 the bandwidth of its predecessor.
![]() |
Integrated Memory Controller
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Expansions[edit]
With the SC3, PEZY plans to replace the previous PCIe interface with a custom optics interface featuring 128 lanes supporting a bandwidth of 256 GB/s.
base frequency | 1,333.333 MHz (1.333 GHz, 1,333,333 kHz) + |
core count | 8,192 + |
core voltage | 0.65 V (6.5 dV, 65 cV, 650 mV) + |
designer | PEZY + |
die area | 700 mm² (1.085 in², 7 cm², 700,000,000 µm²) + |
family | PEZY-SCx + |
first announced | 2016 + |
first launched | 2019 + |
full page name | pezy/pezy-scx/pezy-sc3 + |
has ecc memory support | true + and false + |
instance of | microprocessor + |
ldate | 3000 + |
manufacturer | TSMC + |
market segment | Supercomputer + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + and 11,448.32 GiB/s (11,723,079.68 MiB/s, 12,292.54 GB/s, 12,292,539.999 MB/s, 11.18 TiB/s, 12.293 TB/s) + |
max memory channels | 4 + and 8 + |
model number | PEZY-SC3 + |
name | PEZY-SC3 + |
peak flops (double-precision) | 21,845,333,327,872 FLOPS (21,845,333,327.872 KFLOPS, 21,845,333.328 MFLOPS, 21,845.333 GFLOPS, 21.845 TFLOPS, 0.0218 PFLOPS, 2.184533e-5 EFLOPS, 2.184533e-8 ZFLOPS) + |
peak flops (half-precision) | 87,381,333,311,488 FLOPS (87,381,333,311.488 KFLOPS, 87,381,333.311 MFLOPS, 87,381.333 GFLOPS, 87.381 TFLOPS, 0.0874 PFLOPS, 8.738133e-5 EFLOPS, 8.738133e-8 ZFLOPS) + |
peak flops (single-precision) | 43,690,666,655,744 FLOPS (43,690,666,655.744 KFLOPS, 43,690,666.656 MFLOPS, 43,690.667 GFLOPS, 43.691 TFLOPS, 0.0437 PFLOPS, 4.369067e-5 EFLOPS, 4.369067e-8 ZFLOPS) + |
power dissipation | 400 W (400,000 mW, 0.536 hp, 0.4 kW) + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |
supported memory type | DDR4-3600 + |
technology | CMOS + |
thread count | 65,536 + |