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Difference between revisions of "intel/xeon e5/e5-2667 v4"
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{{intel title|Xeon E5-2667 v4}} | {{intel title|Xeon E5-2667 v4}} | ||
− | {{ | + | {{chip |
| name = Xeon E5-2667 v4 | | name = Xeon E5-2667 v4 | ||
| no image = Yes | | no image = Yes | ||
Line 10: | Line 10: | ||
| model number = E5-2667 v4 | | model number = E5-2667 v4 | ||
| part number = CM8066002041900 | | part number = CM8066002041900 | ||
− | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Server | | market = Server | ||
| first announced = June 20, 2016 | | first announced = June 20, 2016 | ||
Line 26: | Line 26: | ||
| turbo frequency = Yes | | turbo frequency = Yes | ||
| turbo frequency1 = 3,600 MHz | | turbo frequency1 = 3,600 MHz | ||
− | | turbo frequency2 = | + | | turbo frequency2 = 3,600 MHz |
+ | | turbo frequency3 = 3,500 MHz | ||
+ | | turbo frequency4 = 3,500 MHz | ||
+ | | turbo frequency5 = 3,500 MHz | ||
+ | | turbo frequency6 = 3,500 MHz | ||
+ | | turbo frequency7 = 3,500 MHz | ||
+ | | turbo frequency8 = 3,500 MHz | ||
| bus type = QPI | | bus type = QPI | ||
| bus speed = 4,800 MHz | | bus speed = 4,800 MHz | ||
Line 34: | Line 40: | ||
| s-spec = SR2P5 | | s-spec = SR2P5 | ||
| s-spec es = | | s-spec es = | ||
− | | s-spec qs = | + | | s-spec qs = QKF0 |
| cpuid = 406F1 | | cpuid = 406F1 | ||
+ | | isa family = x86 | ||
+ | | isa = x86-64 | ||
| microarch = Broadwell | | microarch = Broadwell | ||
| platform = Grantley EP 2S | | platform = Grantley EP 2S | ||
Line 54: | Line 62: | ||
| max memory = 1,536 GiB | | max memory = 1,536 GiB | ||
− | + | ||
| v core = 1.82 V | | v core = 1.82 V | ||
| v core tolerance = | | v core tolerance = | ||
Line 101: | Line 109: | ||
|l2 extra=(per core, write-back) | |l2 extra=(per core, write-back) | ||
|l3 cache=25 MiB | |l3 cache=25 MiB | ||
− | |l3 break= | + | |l3 break=10x2.5 MiB |
|l3 desc=20-way set associative | |l3 desc=20-way set associative | ||
|l3 extra=(shared, per core, write-back) | |l3 extra=(shared, per core, write-back) | ||
Line 120: | Line 128: | ||
| max memory = 1,536 GiB | | max memory = 1,536 GiB | ||
| pae = 46 bit | | pae = 46 bit | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 40 | ||
+ | | pcie config = x4 | ||
+ | | pcie config 1 = x8 | ||
+ | | pcie config 2 = x16 | ||
}} | }} | ||
== Features == | == Features == | ||
− | {{ | + | {{x86 features |
| em64t = Yes | | em64t = Yes | ||
| nx = Yes | | nx = Yes |
Latest revision as of 12:13, 1 August 2019
Edit Values | |
Xeon E5-2667 v4 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | E5-2667 v4 |
Part Number | CM8066002041900 |
S-Spec | SR2P5 QKF0 (QS) |
Market | Server |
Introduction | June 20, 2016 (announced) June 20, 2016 (launched) |
Release Price | $2057.00 |
Shop | Amazon |
General Specs | |
Family | Xeon E5 |
Series | E5-2000 |
Locked | Yes |
Frequency | 3,200 MHz |
Turbo Frequency | Yes |
Turbo Frequency | 3,600 MHz (1 core), 3,600 MHz (2 cores), 3,500 MHz (3 cores), 3,500 MHz (4 cores), 3,500 MHz (5 cores), 3,500 MHz (6 cores), 3,500 MHz (7 cores), 3,500 MHz (8 cores) |
Bus type | QPI |
Bus speed | 4,800 MHz |
Bus rate | 2 × 9.6 GT/s |
Clock multiplier | 32 |
CPUID | 406F1 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Broadwell |
Platform | Grantley EP 2S |
Chipset | C610 Series |
Core Name | Broadwell EP |
Core Family | 6 |
Core Model | 4F |
Core Stepping | R0 |
Process | 14 nm |
Transistors | 3,200,000,000 |
Technology | CMOS |
Die | 246.24 mm² |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 1,536 GiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
Vcore | 1.82 V |
VI/O | 1.2 V ± 3% |
TDP | 135 W |
Tcase | 0 °C – 78 °C |
Tstorage | -25 °C – 125 °C |
The Xeon E5-2667 v4 is a 64-bit octa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for frequency-optimized 2S environments (2U square form factor). Operating at 3.2 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a 14 nm process (based on Broadwell).
Cache[edit]
- Main article: Broadwell § Cache
Cache Info [Edit Values] | ||
L1I$ | 256 KiB 262,144 B 0.25 MiB |
8x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 256 KiB 262,144 B 0.25 MiB |
8x32 KiB 8-way set associative (per core, write-back) |
L2$ | 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB |
8x256 KiB 8-way set associative (per core, write-back) |
L3$ | 25 MiB 25,600 KiB 26,214,400 B 0.0244 GiB |
10x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics[edit]
This microprocessor has no integrated graphics processing unit.
Memory controller[edit]
Integrated Memory Controller | |
Type | DDR4-2400 |
Controllers | 1 |
Channels | 4 |
ECC Support | Yes |
Max bandwidth | 71.53 GiB/s |
Bandwidth (single) | 17.88 GiB/s |
Bandwidth (dual) | 35.76 GiB/s |
Max memory | 1,536 GiB |
Physical Address Extensions | 46 bit |
Expansions[edit]
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Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Xeon E5-2667 v4 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E5-2667 v4 - Intel#io + |
base frequency | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
bus links | 2 + |
bus rate | 9,600 MT/s (9.6 GT/s, 9,600,000 kT/s) + |
bus speed | 4,800 MHz (4.8 GHz, 4,800,000 kHz) + |
bus type | QPI + |
chipset | C610 Series + |
clock multiplier | 32 + |
core count | 8 + |
core family | 6 + |
core model | 4F + |
core name | Broadwell EP + |
core stepping | R0 + |
core voltage | 1.82 V (18.2 dV, 182 cV, 1,820 mV) + |
cpuid | 406F1 + |
designer | Intel + |
die area | 246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) + |
family | Xeon E5 + |
first announced | June 20, 2016 + |
first launched | June 20, 2016 + |
full page name | intel/xeon e5/e5-2667 v4 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
io voltage | 1.2 V (12 dV, 120 cV, 1,200 mV) + |
io voltage tolerance | 3% + |
isa | x86-64 + |
isa family | x86 + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 25 MiB (25,600 KiB, 26,214,400 B, 0.0244 GiB) + |
ldate | June 20, 2016 + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 351.15 K (78 °C, 172.4 °F, 632.07 °R) + |
max cpu count | 2 + |
max memory | 1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) + |
max pcie lanes | 40 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Broadwell + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | E5-2667 v4 + |
name | Xeon E5-2667 v4 + |
part number | CM8066002041900 + |
platform | Grantley EP 2S + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 2,057.00 (€ 1,851.30, £ 1,666.17, ¥ 212,549.81) + |
s-spec | SR2P5 + |
s-spec (qs) | QKF0 + |
series | E5-2000 + |
smp max ways | 2 + |
tdp | 135 W (135,000 mW, 0.181 hp, 0.135 kW) + |
technology | CMOS + |
thread count | 16 + |
transistor count | 3,200,000,000 + |
turbo frequency (1 core) | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + |
turbo frequency (2 cores) | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + |
turbo frequency (3 cores) | 3,500 MHz (3.5 GHz, 3,500,000 kHz) + |
turbo frequency (4 cores) | 3,500 MHz (3.5 GHz, 3,500,000 kHz) + |
turbo frequency (5 cores) | 3,500 MHz (3.5 GHz, 3,500,000 kHz) + |
turbo frequency (6 cores) | 3,500 MHz (3.5 GHz, 3,500,000 kHz) + |
turbo frequency (7 cores) | 3,500 MHz (3.5 GHz, 3,500,000 kHz) + |
turbo frequency (8 cores) | 3,500 MHz (3.5 GHz, 3,500,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |