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Difference between revisions of "intel/microarchitectures/cooper lake"
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== Release Dates == | == Release Dates == | ||
| − | Cooper Lake is expected to be released in | + | [[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|{{\\|Cooper Lake}} and Ice Lake roadmap.]] |
| + | Cooper Lake is expected to be released in the first half of 2020. | ||
== Process Technology == | == Process Technology == | ||
Revision as of 14:13, 21 May 2019
| Edit Values | |
| Cooper Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2019 |
| Process | 14 nm |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 14-19 |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512 |
| Cache | |
| L1I Cache | 32 KiB/core 8-way set associative |
| L1D Cache | 32 KiB/core 8-way set associative |
| L2 Cache | 1 MiB/core 16-way set associative |
| L3 Cache | 1.375 MiB/core 11-way set associative |
| Cores | |
| Core Names | Cooper Lake X, Cooper Lake SP, Cooper Lake AP |
| Succession | |
| Contemporary | |
| Coffee Lake | |
Cooper Lake (CPL) is Intel's successor to Cascade Lake, a 14 nm microarchitecture for enthusiasts and servers.
For desktop enthusiasts, Cascade Lake is branded Core i7, and Core i9 processors (under the Core X series). For scalable server class processors, Intel branded it as Xeon Bronze, Xeon Silver, Xeon Gold, and Xeon Platinum.
Contents
Codenames
| Core | Abbrev | Target |
|---|---|---|
| Cooper Lake X | CPL-X | High-end desktops & enthusiasts market |
| Cooper Lake W | CPL-W | Enterprise/Business workstations |
| Cooper Lake SP | CPL-SP | Server Scalable Processors |
| Cooper Lake AP | CPL-AP | Server Advanced Processors |
Brands
 |
This section is empty; you can help add the missing info by editing this page. |
Release Dates
Cooper Lake is expected to be released in the first half of 2020.
Process Technology
Cooper Lake is fabricated on Intel's 3rd generation enhanced 14nm++ process.
Architecture
Cooper Lake is based on the Whitley platform.
Key changes from Cascade Lake
- SoC
- Higher core count (??, up from 28)
- I/O
- PCIe 4.0 (from PCIe 3.0)
- Memory
- Higher bandwidth (174.84 GiB/s, up from 119.209 GiB/s)
- Octa-channel (up from hexa-channel)
- Optane DC DIMMs
- Apache Pass → Barlow Pass
- Platform
- Packaging
- 4189-contact flip-chip LGA (up from 3647 contacts)
This list is incomplete; you can help by expanding it.
New instructions
Cooper Lake introduced a number of new instructions:
- BFLOAT16 - A new data type for acceleration of AI workloads.
- AVX512 BF16 - AVX-512 Brain Float 16 extension
See also
Facts about "Cooper Lake - Microarchitectures - Intel"
| codename | Cooper Lake + |
| designer | Intel + |
| first launched | 2019 + |
| full page name | intel/microarchitectures/cooper lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Cooper Lake + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |