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Difference between revisions of "intel/xeon platinum/8170m"
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{{intel title|Xeon Platinum 8170M}} | {{intel title|Xeon Platinum 8170M}} | ||
− | {{ | + | {{chip |
− | |||
|name=Xeon Platinum 8170M | |name=Xeon Platinum 8170M | ||
− | | | + | |image=skylake sp (basic).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
Line 9: | Line 8: | ||
|part number=CD8067303319201 | |part number=CD8067303319201 | ||
|s-spec=SR3BD | |s-spec=SR3BD | ||
+ | |s-spec qs=QMQ3 | ||
|market=Server | |market=Server | ||
|first announced=April 25, 2017 | |first announced=April 25, 2017 | ||
+ | |first launched=July 11, 2017 | ||
+ | |release price=$10409.00 | ||
|family=Xeon Platinum | |family=Xeon Platinum | ||
− | |series= | + | |series=8000 |
− | + | |frequency=2,100 MHz | |
− | |frequency=2 | + | |turbo frequency1=3,700 MHz |
− | | | ||
− | |||
− | |||
|clock multiplier=21 | |clock multiplier=21 | ||
+ | |cpuid=0x50654 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch=Skylake | + | |microarch=Skylake (server) |
|platform=Purley | |platform=Purley | ||
|chipset=Lewisburg | |chipset=Lewisburg | ||
Line 29: | Line 29: | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
− | |||
|word size=64 bit | |word size=64 bit | ||
+ | |core count=26 | ||
+ | |thread count=52 | ||
|max cpus=8 | |max cpus=8 | ||
− | | | + | |max memory=1,536 GiB |
− | | | + | |tdp=165 W |
− | | | + | |tcase min=0 °C |
− | | | + | |tcase max=89 °C |
− | | | + | |dts min=0 °C |
− | |package | + | |dts max=99 °C |
+ | |package name 1=intel,fclga_3647 | ||
}} | }} | ||
− | '''Xeon Platinum 8170M''' is a {{arch|64}} [[x86]] | + | '''Xeon Platinum 8170M''' is a {{arch|64}} [[26-core]] [[x86]] multi-socket highest performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8170M, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 165 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 1.5 TiB of hexa-channel DDR4-2666 ECC memory. |
+ | As indicated by the ''M'' suffix, this specific model supports double the memory capacity for up to 1.5 TiB per socket. | ||
− | {{ | + | == Cache == |
+ | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=1.625 MiB | ||
+ | |l1i cache=832 KiB | ||
+ | |l1i break=26x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=832 KiB | ||
+ | |l1d break=26x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=26 MiB | ||
+ | |l2 break=26x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=35.75 MiB | ||
+ | |l3 break=26x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=Yes | ||
+ | |max mem=1,536 GiB | ||
+ | |controllers=2 | ||
+ | |channels=6 | ||
+ | |max bandwidth=119.21 GiB/s | ||
+ | |bandwidth schan=19.87 GiB/s | ||
+ | |bandwidth dchan=39.74 GiB/s | ||
+ | |bandwidth qchan=79.47 GiB/s | ||
+ | |bandwidth hchan=119.21 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 48 | ||
+ | | pcie config = x16 | ||
+ | | pcie config 2 = x8 | ||
+ | | pcie config 3 = x4 | ||
+ | }} | ||
== Features == | == Features == | ||
Line 65: | Line 110: | ||
|avx=Yes | |avx=Yes | ||
|avx2=Yes | |avx2=Yes | ||
− | | | + | |avx512f=Yes |
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No | ||
Line 80: | Line 136: | ||
|f16c=Yes | |f16c=Yes | ||
|tbt1=No | |tbt1=No | ||
− | |tbt2= | + | |tbt2=Yes |
|tbmt3=No | |tbmt3=No | ||
|bpt=No | |bpt=No | ||
|eist=Yes | |eist=Yes | ||
− | |sst= | + | |sst=Yes |
|flex=No | |flex=No | ||
|fastmem=No | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=Yes | ||
+ | |intelnode=Yes | ||
+ | |kpt=Yes | ||
+ | |ptt=Yes | ||
+ | |intelrunsure=Yes | ||
+ | |mbe=Yes | ||
|isrt=No | |isrt=No | ||
|sba=No | |sba=No | ||
Line 94: | Line 157: | ||
|ipt=No | |ipt=No | ||
|tsx=Yes | |tsx=Yes | ||
− | |txt= | + | |txt=Yes |
|ht=Yes | |ht=Yes | ||
|vpro=Yes | |vpro=Yes | ||
Line 100: | Line 163: | ||
|vtd=Yes | |vtd=Yes | ||
|ept=Yes | |ept=Yes | ||
− | |mpx= | + | |mpx=No |
|sgx=No | |sgx=No | ||
|securekey=No | |securekey=No | ||
− | |osguard= | + | |osguard=No |
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
Line 110: | Line 173: | ||
|amdvi=No | |amdvi=No | ||
|amdv=No | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
|rvi=No | |rvi=No | ||
|smt=No | |smt=No | ||
Line 115: | Line 181: | ||
|xfr=No | |xfr=No | ||
}} | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=2,100 MHz | ||
+ | |freq_1=3,700 MHz | ||
+ | |freq_2=3,700 MHz | ||
+ | |freq_3=3,500 MHz | ||
+ | |freq_4=3,500 MHz | ||
+ | |freq_5=3,400 MHz | ||
+ | |freq_6=3,400 MHz | ||
+ | |freq_7=3,400 MHz | ||
+ | |freq_8=3,400 MHz | ||
+ | |freq_9=3,400 MHz | ||
+ | |freq_10=3,400 MHz | ||
+ | |freq_11=3,400 MHz | ||
+ | |freq_12=3,400 MHz | ||
+ | |freq_13=3,300 MHz | ||
+ | |freq_14=3,300 MHz | ||
+ | |freq_15=3,300 MHz | ||
+ | |freq_16=3,300 MHz | ||
+ | |freq_17=3,000 MHz | ||
+ | |freq_18=3,000 MHz | ||
+ | |freq_19=3,000 MHz | ||
+ | |freq_20=3,000 MHz | ||
+ | |freq_21=2,800 MHz | ||
+ | |freq_22=2,800 MHz | ||
+ | |freq_23=2,800 MHz | ||
+ | |freq_24=2,800 MHz | ||
+ | |freq_25=2,800 MHz | ||
+ | |freq_26=2,800 MHz | ||
+ | |freq_avx2_base=1,700 MHz | ||
+ | |freq_avx2_1=3,600 MHz | ||
+ | |freq_avx2_2=3,600 MHz | ||
+ | |freq_avx2_3=3,400 MHz | ||
+ | |freq_avx2_4=3,400 MHz | ||
+ | |freq_avx2_5=3,300 MHz | ||
+ | |freq_avx2_6=3,300 MHz | ||
+ | |freq_avx2_7=3,300 MHz | ||
+ | |freq_avx2_8=3,300 MHz | ||
+ | |freq_avx2_9=3,200 MHz | ||
+ | |freq_avx2_10=3,200 MHz | ||
+ | |freq_avx2_11=3,200 MHz | ||
+ | |freq_avx2_12=3,200 MHz | ||
+ | |freq_avx2_13=2,800 MHz | ||
+ | |freq_avx2_14=2,800 MHz | ||
+ | |freq_avx2_15=2,800 MHz | ||
+ | |freq_avx2_16=2,800 MHz | ||
+ | |freq_avx2_17=2,600 MHz | ||
+ | |freq_avx2_18=2,600 MHz | ||
+ | |freq_avx2_19=2,600 MHz | ||
+ | |freq_avx2_20=2,600 MHz | ||
+ | |freq_avx2_21=2,400 MHz | ||
+ | |freq_avx2_22=2,400 MHz | ||
+ | |freq_avx2_23=2,400 MHz | ||
+ | |freq_avx2_24=2,400 MHz | ||
+ | |freq_avx2_25=2,400 MHz | ||
+ | |freq_avx2_26=2,400 MHz | ||
+ | |freq_avx512_base=1,300 MHz | ||
+ | |freq_avx512_1=3,500 MHz | ||
+ | |freq_avx512_2=3,500 MHz | ||
+ | |freq_avx512_3=3,300 MHz | ||
+ | |freq_avx512_4=3,300 MHz | ||
+ | |freq_avx512_5=2,900 MHz | ||
+ | |freq_avx512_6=2,900 MHz | ||
+ | |freq_avx512_7=2,900 MHz | ||
+ | |freq_avx512_8=2,900 MHz | ||
+ | |freq_avx512_9=2,500 MHz | ||
+ | |freq_avx512_10=2,500 MHz | ||
+ | |freq_avx512_11=2,500 MHz | ||
+ | |freq_avx512_12=2,500 MHz | ||
+ | |freq_avx512_13=2,200 MHz | ||
+ | |freq_avx512_14=2,200 MHz | ||
+ | |freq_avx512_15=2,200 MHz | ||
+ | |freq_avx512_16=2,200 MHz | ||
+ | |freq_avx512_17=2,100 MHz | ||
+ | |freq_avx512_18=2,100 MHz | ||
+ | |freq_avx512_19=2,100 MHz | ||
+ | |freq_avx512_20=2,100 MHz | ||
+ | |freq_avx512_21=1,900 MHz | ||
+ | |freq_avx512_22=1,900 MHz | ||
+ | |freq_avx512_23=1,900 MHz | ||
+ | |freq_avx512_24=1,900 MHz | ||
+ | |freq_avx512_25=1,900 MHz | ||
+ | |freq_avx512_26=1,900 MHz | ||
+ | }} | ||
+ | |||
+ | [[Category:microprocessor models by intel based on skylake extreme core count die]] |
Latest revision as of 14:23, 8 May 2019
Edit Values | |
Xeon Platinum 8170M | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 8170M |
Part Number | CD8067303319201 |
S-Spec | SR3BD QMQ3 (QS) |
Market | Server |
Introduction | April 25, 2017 (announced) July 11, 2017 (launched) |
Release Price | $10409.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Platinum |
Series | 8000 |
Frequency | 2,100 MHz |
Turbo Frequency | 3,700 MHz (1 core) |
Clock multiplier | 21 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | H0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 26 |
Threads | 52 |
Max Memory | 1,536 GiB |
Multiprocessing | |
Max SMP | 8-Way (Multiprocessor) |
Electrical | |
TDP | 165 W |
Tcase | 0 °C – 89 °C |
TDTS | 0 °C – 99 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Xeon Platinum 8170M is a 64-bit 26-core x86 multi-socket highest performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8170M, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.1 GHz with a TDP of 165 W and a turbo boost frequency of up to 3.7 GHz, supports up 1.5 TiB of hexa-channel DDR4-2666 ECC memory.
As indicated by the M suffix, this specific model supports double the memory capacity for up to 1.5 TiB per socket.
Cache[edit]
- Main article: Skylake § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | ||
Normal | 2,100 MHz | 3,700 MHz | 3,700 MHz | 3,500 MHz | 3,500 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,000 MHz | 3,000 MHz | 3,000 MHz | 3,000 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz |
AVX2 | 1,700 MHz | 3,600 MHz | 3,600 MHz | 3,400 MHz | 3,400 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,200 MHz | 3,200 MHz | 3,200 MHz | 3,200 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz |
AVX512 | 1,300 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz | 2,900 MHz | 2,900 MHz | 2,900 MHz | 2,900 MHz | 2,500 MHz | 2,500 MHz | 2,500 MHz | 2,500 MHz | 2,200 MHz | 2,200 MHz | 2,200 MHz | 2,200 MHz | 2,100 MHz | 2,100 MHz | 2,100 MHz | 2,100 MHz | 1,900 MHz | 1,900 MHz | 1,900 MHz | 1,900 MHz | 1,900 MHz | 1,900 MHz |
Facts about "Xeon Platinum 8170M - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Platinum 8170M - Intel#io + |
base frequency | 2,100 MHz (2.1 GHz, 2,100,000 kHz) + |
chipset | Lewisburg + |
clock multiplier | 21 + |
core count | 26 + |
core family | 6 + |
core name | Skylake SP + |
core stepping | H0 + |
cpuid | 0x50654 + |
designer | Intel + |
family | Xeon Platinum + |
first announced | April 25, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon platinum/8170m + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,664 KiB (1,703,936 B, 1.625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 832 KiB (851,968 B, 0.813 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 832 KiB (851,968 B, 0.813 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 26 MiB (26,624 KiB, 27,262,976 B, 0.0254 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 35.75 MiB (36,608 KiB, 37,486,592 B, 0.0349 GiB) + |
ldate | July 11, 2017 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 362.15 K (89 °C, 192.2 °F, 651.87 °R) + |
max cpu count | 8 + |
max dts temperature | 99 °C + |
max memory | 1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min dts temperature | 0 °C + |
model number | 8170M + |
name | Xeon Platinum 8170M + |
package | FCLGA-3647 + |
part number | CD8067303319201 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 10,409.00 (€ 9,368.10, £ 8,431.29, ¥ 1,075,561.97) + |
s-spec | SR3BD + |
s-spec (qs) | QMQ3 + |
series | 8000 + |
smp max ways | 8 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2666 + |
tdp | 165 W (165,000 mW, 0.221 hp, 0.165 kW) + |
technology | CMOS + |
thread count | 52 + |
turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |