Semiconductor & Computer Engineering
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Difference between revisions of "chip multiprocessor"
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== Overview == | == Overview == | ||
{{empty section}} | {{empty section}} | ||
| + | |||
| + | === Heterogeneous multi-core architectures === | ||
| + | {{empty section}} | ||
| + | |||
| + | ==== Single and Multi-ISA designs ==== | ||
| + | {{empty section}} | ||
| + | |||
| + | == Multi-core chips == | ||
| + | {{collist | ||
| + | | count = 5 | ||
| + | | | ||
| + | * {{\\|2|2 (dual-core)}} | ||
| + | * {{\\|3|3 (tri-Core)}} | ||
| + | * {{\\|4|4 (quad-core)}} | ||
| + | * {{\\|5|5 (penta-core)}} | ||
| + | * {{\\|6|6 (hexa-core)}} | ||
| + | * {{\\|7|7 (hepta-core)}} | ||
| + | * {{\\|8|8 (octa-core)}} | ||
| + | * {{\\|9|9 (nona-core)}} | ||
| + | * {{\\|10|10 (deca-core)}} | ||
| + | * {{\\|11|11 (undeca-core)}} | ||
| + | * {{\\|12|12 (dodeca-core)}} | ||
| + | * {{\\|13|13 (trideca-core)}} | ||
| + | * {{\\|14|14 (tetradeca-core)}} | ||
| + | * {{\\|15|15 (pentadeca-core)}} | ||
| + | * {{\\|16|16 (hexadeca-core)}} | ||
| + | * {{\\|17|17 (heptadeca-core)}} | ||
| + | * {{\\|18|18 (octadeca-core)}} | ||
| + | * {{\\|19|19 (nonadeca-core)}} | ||
| + | * {{\\|20|20 (icosa-core)}} | ||
| + | * {{\\|21|21 (henicosa-core)}} | ||
| + | * {{\\|22|22 (docosa-core)}} | ||
| + | * {{\\|23|23 (tricosa-core)}} | ||
| + | * {{\\|24|24 (tetracosa-core)}} | ||
| + | * {{\\|25|25 (pentacosa-core)}} | ||
| + | * {{\\|26|26 (hexacosa-core)}} | ||
| + | * {{\\|27|27 (heptacosa-core)}} | ||
| + | * {{\\|28|28 (octacosa-core)}} | ||
| + | * {{\\|29|29 (nonacosa-core)}} | ||
| + | * {{\\|30|30 (triaconta-core)}} | ||
| + | * {{\\|32|32 (dotriaconta-core)}} | ||
| + | * {{\\|40|40 (tetraconta-core)}} | ||
| + | * {{\\|46|46 (hexatetraconta-core)}} | ||
| + | * {{\\|48|48 (octatetraconta-core)}} | ||
| + | * {{\\|64|64 (tetrahexaconta-core)}} | ||
| + | * {{\\|1000|1000 (kilo-core)}} | ||
| + | * {{\\|128|128 (octacosahecta-core)}} | ||
| + | }} | ||
| + | |||
| + | == See also == | ||
| + | * [[single-core]] | ||
| + | * [[big core]] | ||
| + | * [[small core]] | ||
| + | * [[chiplet]] | ||
| + | |||
{{stub}} | {{stub}} | ||
Revision as of 23:55, 20 February 2019
A chip multiprocessor (CMP) or multi-core architecture is a logic design architecture whereby multiple processing units (e.g., CPU cores) are integrated onto a single monolithic integrated circuit or onto multiple dies in a single package.
Contents
History
 |
This section is empty; you can help add the missing info by editing this page. |
Overview
| |
This section is empty; you can help add the missing info by editing this page. |
Heterogeneous multi-core architectures
| |
This section is empty; you can help add the missing info by editing this page. |
Single and Multi-ISA designs
| |
This section is empty; you can help add the missing info by editing this page. |
Multi-core chips
- 2 (dual-core)
- 3 (tri-Core)
- 4 (quad-core)
- 5 (penta-core)
- 6 (hexa-core)
- 7 (hepta-core)
- 8 (octa-core)
- 9 (nona-core)
- 10 (deca-core)
- 11 (undeca-core)
- 12 (dodeca-core)
- 13 (trideca-core)
- 14 (tetradeca-core)
- 15 (pentadeca-core)
- 16 (hexadeca-core)
- 17 (heptadeca-core)
- 18 (octadeca-core)
- 19 (nonadeca-core)
- 20 (icosa-core)
- 21 (henicosa-core)
- 22 (docosa-core)
- 23 (tricosa-core)
- 24 (tetracosa-core)
- 25 (pentacosa-core)
- 26 (hexacosa-core)
- 27 (heptacosa-core)
- 28 (octacosa-core)
- 29 (nonacosa-core)
- 30 (triaconta-core)
- 32 (dotriaconta-core)
- 40 (tetraconta-core)
- 46 (hexatetraconta-core)
- 48 (octatetraconta-core)
- 64 (tetrahexaconta-core)
- 1000 (kilo-core)
- 128 (octacosahecta-core)
See also
 |
This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information. |