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Difference between revisions of "intel/celeron/3865u"
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{{intel title|Celeron 3865U}} | {{intel title|Celeron 3865U}} | ||
− | {{ | + | {{chip |
− | | name | + | |name=Celeron 3865U |
− | | no image | + | |no image=Yes |
− | + | |designer=Intel | |
− | + | |manufacturer=Intel | |
− | + | |model number=3865U | |
− | | designer | + | |s-spec=SR349 |
− | | manufacturer | + | |market=Mobile |
− | | model number | + | |first announced=January 3, 2017 |
− | + | |first launched=January 3, 2017 | |
− | + | |family=Celeron | |
− | | s-spec | + | |series=3800 |
− | | market | + | |locked=Yes |
− | | first announced | + | |frequency=1,800 MHz |
− | | first launched | + | |bus type=OPI |
− | + | |bus rate=4 GT/s | |
− | + | |clock multiplier=22 | |
− | + | |cpuid=806E9 | |
− | + | |isa=x86-64 | |
− | | family | + | |isa family=x86 |
− | | series | + | |microarch=Kaby Lake |
− | | locked | + | |platform=Kaby Lake |
− | | frequency | + | |core name=Kaby Lake U |
− | | bus type | + | |core family=6 |
− | + | |core model=142 | |
− | | bus rate | + | |core stepping=H0 |
− | + | |process=14 nm | |
− | | clock multiplier | + | |technology=CMOS |
− | | cpuid | + | |word size=64 bit |
− | + | |core count=2 | |
− | | isa | + | |thread count=2 |
− | | isa | + | |max cpus=1 |
− | | microarch | + | |max memory=64 GiB |
− | | platform | + | |v core min=0.25 V |
− | + | |v core max=1.52 V | |
− | + | |tdp=15 W | |
− | | core name | + | |ctdp down=10 W |
− | | core family | + | |tjunc min=0 °C |
− | | core model | + | |tjunc max=100 °C |
− | + | |tstorage min=-25 °C | |
− | | core stepping | + | |tstorage max=125 °C |
− | | process | + | |package module 1={{packages/intel/fcbga-1356}} |
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− | | technology | ||
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− | | word size | ||
− | | core count | ||
− | | thread count | ||
− | | max cpus | ||
− | | max memory | ||
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− | | v core min | ||
− | | v core max | ||
− | | tdp | ||
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− | | ctdp down | ||
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− | | tjunc min | ||
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}} | }} | ||
'''Celeron 3865U''' is a {{arch|64}} [[dual-core]] budget [[x86]] mobile microprocessors introduced by [[Intel]] in early 2017. The 3865U, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14nm+ process]]. This processor operates at 1.8 GHz with a TDP of 15 W and supports up to 32 GiB of dual-channel non-ECC DDR4-2133. Additionally the 3865U incorporates Intel's {{intel|HD Graphics 610}} [[IGP]] operating at 300 MHz with a burst frequency of 900 GHz. | '''Celeron 3865U''' is a {{arch|64}} [[dual-core]] budget [[x86]] mobile microprocessors introduced by [[Intel]] in early 2017. The 3865U, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14nm+ process]]. This processor operates at 1.8 GHz with a TDP of 15 W and supports up to 32 GiB of dual-channel non-ECC DDR4-2133. Additionally the 3865U incorporates Intel's {{intel|HD Graphics 610}} [[IGP]] operating at 300 MHz with a burst frequency of 900 GHz. | ||
+ | This model has a configurable TDP-down of 10 W. | ||
== Cache == | == Cache == | ||
{{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}} | {{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}} | ||
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|l1i break=2x32 KiB | |l1i break=2x32 KiB | ||
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
− | |||
|l1d cache=64 KiB | |l1d cache=64 KiB | ||
|l1d break=2x32 KiB | |l1d break=2x32 KiB | ||
Line 151: | Line 115: | ||
| hdmi ver = 1.4a | | hdmi ver = 1.4a | ||
| dp ver = 1.2 | | dp ver = 1.2 | ||
− | | edp ver = 1. | + | | edp ver = 1.4 |
| max res hdmi = 4096x2304 | | max res hdmi = 4096x2304 | ||
| max res hdmi freq = 24 Hz | | max res hdmi freq = 24 Hz | ||
Line 170: | Line 134: | ||
| intel clear video hd = Yes | | intel clear video hd = Yes | ||
}} | }} | ||
+ | {{kaby lake hardware accelerated video table|col=1}} | ||
== Features == | == Features == | ||
Line 194: | Line 159: | ||
|avx=No | |avx=No | ||
|avx2=No | |avx2=No | ||
− | + | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No |
Latest revision as of 09:08, 11 February 2019
Edit Values | |||||||||||||
Celeron 3865U | |||||||||||||
General Info | |||||||||||||
Designer | Intel | ||||||||||||
Manufacturer | Intel | ||||||||||||
Model Number | 3865U | ||||||||||||
S-Spec | SR349 | ||||||||||||
Market | Mobile | ||||||||||||
Introduction | January 3, 2017 (announced) January 3, 2017 (launched) | ||||||||||||
Shop | Amazon | ||||||||||||
General Specs | |||||||||||||
Family | Celeron | ||||||||||||
Series | 3800 | ||||||||||||
Locked | Yes | ||||||||||||
Frequency | 1,800 MHz | ||||||||||||
Bus type | OPI | ||||||||||||
Bus rate | 4 GT/s | ||||||||||||
Clock multiplier | 22 | ||||||||||||
CPUID | 806E9 | ||||||||||||
Microarchitecture | |||||||||||||
ISA | x86-64 (x86) | ||||||||||||
Microarchitecture | Kaby Lake | ||||||||||||
Platform | Kaby Lake | ||||||||||||
Core Name | Kaby Lake U | ||||||||||||
Core Family | 6 | ||||||||||||
Core Model | 142 | ||||||||||||
Core Stepping | H0 | ||||||||||||
Process | 14 nm | ||||||||||||
Technology | CMOS | ||||||||||||
Word Size | 64 bit | ||||||||||||
Cores | 2 | ||||||||||||
Threads | 2 | ||||||||||||
Max Memory | 64 GiB | ||||||||||||
Multiprocessing | |||||||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||||||
Electrical | |||||||||||||
Vcore | 0.25 V-1.52 V | ||||||||||||
TDP | 15 W | ||||||||||||
cTDP down | 10 W | ||||||||||||
Tjunction | 0 °C – 100 °C | ||||||||||||
Tstorage | -25 °C – 125 °C | ||||||||||||
Packaging | |||||||||||||
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Celeron 3865U is a 64-bit dual-core budget x86 mobile microprocessors introduced by Intel in early 2017. The 3865U, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14nm+ process. This processor operates at 1.8 GHz with a TDP of 15 W and supports up to 32 GiB of dual-channel non-ECC DDR4-2133. Additionally the 3865U incorporates Intel's HD Graphics 610 IGP operating at 300 MHz with a burst frequency of 900 GHz.
This model has a configurable TDP-down of 10 W.
Cache[edit]
- Main article: Kaby Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Graphics[edit]
Integrated Graphics Information
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[Edit] Kaby Lake (Gen9.5) Hardware Accelerated Video Capabilities | |||||||
---|---|---|---|---|---|---|---|
Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, MVC, Stereo | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main, Main 10 | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | 3840x3840 | |||
VP8 | Unified | Unified | N/A | 0 | Unified | 1080p | |
VP9 | 0 | 2160p (4K) | 0, 2 | Unified | 2160p (4K) |
Features[edit]
[Edit/Modify Supported Features]
Facts about "Celeron 3865U - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron 3865U - Intel#io + |
device id | 0x5906 + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology + and My WiFi Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel my wifi technology support | true + |
has intel secure key technology | true + |
has intel smart response technology support | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has x86 advanced encryption standard instruction set extension | true + |
integrated gpu | HD Graphics 610 + |
integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 12 + |
integrated gpu max frequency | 900 MHz (0.9 GHz, 900,000 KHz) + |
integrated gpu max memory | 32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
supported memory type | LPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |