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{{ibm title|POWER9 02CY771}} | {{ibm title|POWER9 02CY771}} | ||
− | {{chip}} | + | {{chip |
+ | |name=02CY771 | ||
+ | |no image=Yes | ||
+ | |designer=IBM | ||
+ | |manufacturer=GlobalFoundries | ||
+ | |model number=02CY771 | ||
+ | |part number=02CY771 | ||
+ | |market=Server | ||
+ | |market 2=Workstation | ||
+ | |first announced=November, 2017 | ||
+ | |first launched=November, 2017 | ||
+ | |family=POWER | ||
+ | |series=POWER9 | ||
+ | |frequency=2.20 GHz | ||
+ | |turbo frequency=3.80 GHz | ||
+ | |isa=Power ISA v3.0B | ||
+ | |isa family=Power ISA | ||
+ | |microarch=POWER9 | ||
+ | |core name=Sforza | ||
+ | |process=14 nm | ||
+ | |transistors=8,000,000,000 | ||
+ | |technology=CMOS | ||
+ | |die area=693.37 mm² | ||
+ | |die length=25.228 mm | ||
+ | |die width=27.48416 mm | ||
+ | |word size=64 bit | ||
+ | |core count=12 | ||
+ | |thread count=48 | ||
+ | |max cpus=2 | ||
+ | |max memory=2 TiB | ||
+ | |tdp=105 W | ||
+ | |tjunc min=0 °C | ||
+ | |tjunc max=85 °C | ||
+ | |package name 1=ibm,fclga_2601 | ||
+ | }} | ||
'''POWER9 02CY771''' is a [[12-core]] [[POWER]] server and workstation microprocessor designed by [[IBM]] and introduced in late [[2017]]. This chip is based on the {{ibm|POWER9|l=arch}} microarchitecture and is fabricated on GlobalFoundries [[14 nm process|14nm SOI Process]]. The 02CY771 has a base frequency of 2.2 GHz with a bost frequency of 3.80 GHz and a TDP of 105 W. | '''POWER9 02CY771''' is a [[12-core]] [[POWER]] server and workstation microprocessor designed by [[IBM]] and introduced in late [[2017]]. This chip is based on the {{ibm|POWER9|l=arch}} microarchitecture and is fabricated on GlobalFoundries [[14 nm process|14nm SOI Process]]. The 02CY771 has a base frequency of 2.2 GHz with a bost frequency of 3.80 GHz and a TDP of 105 W. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|ibm/microarchitectures/power9#Memory_Hierarchy|l1=POWER9 § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=768 KiB | ||
+ | |l1i cache=384 KiB | ||
+ | |l1i break=12x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=384 KiB | ||
+ | |l1d break=12x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l2 cache=3 MiB | ||
+ | |l2 break=6x512 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l3 cache=60 MiB | ||
+ | |l3 break=6x10 MiB | ||
+ | |l3 desc=20-way set associative | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=No | ||
+ | |max mem=2 TiB | ||
+ | |controllers=2 | ||
+ | |channels=8 | ||
+ | |max bandwidth=158.95 GiB/s | ||
+ | |bandwidth schan=19.87 GiB/s | ||
+ | |bandwidth dchan=39.74 GiB/s | ||
+ | |bandwidth qchan=79.47 GiB/s | ||
+ | |bandwidth ochan=158.95 GiB/s | ||
+ | }} | ||
+ | |||
+ | {{ibm power9 sforza memory configs}} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=4.0 | ||
+ | |pcie lanes=48 | ||
+ | |pcie config=x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | == Die == | ||
+ | {{see also|ibm/microarchitectures/power9#Die|l1=POWER9 § Die}} | ||
+ | A die shot of IBM's [[22-core]] server microprocessor used in this part: | ||
+ | |||
+ | : [[File:power9 so die.png|500px]] | ||
+ | |||
+ | |||
+ | : [[File:power9 so die (annotated).png|500px]] |
Latest revision as of 03:54, 17 January 2019
Edit Values | |
02CY771 | |
General Info | |
Designer | IBM |
Manufacturer | GlobalFoundries |
Model Number | 02CY771 |
Part Number | 02CY771 |
Market | Server, Workstation |
Introduction | November, 2017 (announced) November, 2017 (launched) |
General Specs | |
Family | POWER |
Series | POWER9 |
Frequency | 2.20 GHz |
Turbo Frequency | 3.80 GHz |
Microarchitecture | |
ISA | Power ISA v3.0B (Power ISA) |
Microarchitecture | POWER9 |
Core Name | Sforza |
Process | 14 nm |
Transistors | 8,000,000,000 |
Technology | CMOS |
Die | 693.37 mm² 25.228 mm × 27.48416 mm |
Word Size | 64 bit |
Cores | 12 |
Threads | 48 |
Max Memory | 2 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
TDP | 105 W |
Tjunction | 0 °C – 85 °C |
Packaging | |
Package | FCLGA-2601 (PLGA) |
Dimension | 50 mm × 50 mm |
Pitch | 1.016 mm |
Contacts | 2601 |
POWER9 02CY771 is a 12-core POWER server and workstation microprocessor designed by IBM and introduced in late 2017. This chip is based on the POWER9 microarchitecture and is fabricated on GlobalFoundries 14nm SOI Process. The 02CY771 has a base frequency of 2.2 GHz with a bost frequency of 3.80 GHz and a TDP of 105 W.
Contents
Cache[edit]
- Main article: POWER9 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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[Edit] Memory Configurations | |
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Configuration | Speed |
One DIMM per channel | 2666 MHz |
Two DIMMs per channel | 2400 MHz |
Expansions[edit]
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Expansion Options |
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Die[edit]
- See also: POWER9 § Die
A die shot of IBM's 22-core server microprocessor used in this part:
Facts about "POWER9 02CY771 - IBM"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | POWER9 02CY771 - IBM#pcie + |
base frequency | 2,200 MHz (2.2 GHz, 2,200,000 kHz) + |
core count | 12 + |
core name | Sforza + |
designer | IBM + |
die area | 693.37 mm² (1.075 in², 6.934 cm², 693,370,000 µm²) + |
die length | 25.228 mm (2.523 cm, 0.993 in, 25,228 µm) + |
die width | 27.484 mm (2.748 cm, 1.082 in, 27,484.16 µm) + |
family | POWER + |
first announced | November 2017 + |
first launched | November 2017 + |
full page name | ibm/power/02cy771 + |
has ecc memory support | false + |
instance of | microprocessor + |
isa | Power ISA v3.0B + |
isa family | Power ISA + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 60 MiB (61,440 KiB, 62,914,560 B, 0.0586 GiB) + |
ldate | November 2017 + |
manufacturer | GlobalFoundries + |
market segment | Server + and Workstation + |
max cpu count | 2 + |
max junction temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
max memory bandwidth | 158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) + |
max memory channels | 8 + |
microarchitecture | POWER9 + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 02CY771 + |
name | 02CY771 + |
package | FCLGA-2601 + |
part number | 02CY771 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
series | POWER9 + |
smp max ways | 2 + |
supported memory type | DDR4-2666 + |
tdp | 105 W (105,000 mW, 0.141 hp, 0.105 kW) + |
technology | CMOS + |
thread count | 48 + |
transistor count | 8,000,000,000 + |
turbo frequency | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |