Revision as of 07:07, 13 January 2019

Exynos Mongoose 2 (M2) is the successor to the Mongoose 1, a 10 nm ARM microarchitecture designed by Samsung for their consumer electronics.

Process Technology

M2 was fabricated on Samsung's first generation 10LPE (Low Power Early) process.

Compiler support

Architecture

Key changes from Mongoose 1

• 10nm (10LPE) process (from 14 nm)
• Larger ROB (100, up from 96)

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Block Diagram

Core Cluster Overview

(Cluster identical to Mongoose 1)

Individual Core

Memory Hierarchy

• Cache
  • L1I Cache
    • 64 KiB, 4-way set associative
      • 128 B line size
      • per core
    • Parity-protected
  • L1D Cache
    • 32 KiB, 8-way set associative
      • 64 B line size
      • per core
    • 4 cycles for fastest load-to-use
    • 16 B/cycle load bandwidth
    • 16 B/cycle store bandwidth
  • L2 Cache
    • 2 MiB, 16-way set associative
      • 4x banks (512 KiB each)
    • Inclusive of L1
    • 22 cycles latency
    • 16 B/cycle/CPU bandwidth

Mongoose 1 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).

• TLBs
  • ITLB
    • 256-entry
  • DTLB
    • 32-entry
  • STLB
    • 1,024-entry
    • Per core

• BPU
  • 4K-entry main BTB
  • 64-entry µBTB
  • 64-entry return stack

Core

The M2 core appears to be fairly identical to the M1.

All M2 Processors